emmtrix Wiki - User contributions [en]

emmtrix Link Stubber

2025-09-04T08:17:16Z

Mira.steinmetz:

The '''emmtrix Link Stubber''' is a Clang-based tool designed to augment C and C++ source files in a way that makes them linkable, even in the absence of complete implementations. This tool is particularly useful in early development phases, integration testing, unit testing, static analysis, or code generation pipelines where certain source components or libraries may not yet be available.

== Motivation ==

Modern software development — especially in embedded and safety-critical domains — often involves compiling and analyzing incomplete systems. Missing function definitions or global variables can prevent successful linking, which blocks further tool-based processing like:

* Binary generation
* Static timing analysis
* Code instrumentation
* Unit test compilation
* Cross-module analysis

The '''emmtrix Link Stubber''' solves this by generating stub implementations for unresolved symbols, allowing compilation and linking to proceed without requiring full source availability.

== Features ==

* '''Automatic Stub Generation''' Automatically generates minimal placeholder implementations for:
** Undefined functions, member functions, constructors or destructors
** External global or static variables
** Forward-declared classes and structs
** Function and class templates
** Abstract classes (with pure virtuals) are handled by:
*** Finding a suitable concrete derived class
*** Or generating a new one if none exists
* '''Multi-Translation-Unit (TU) Support'''
** Definitions can be generated across multiple input files
** Emits one output file per TU
* '''Clang Integration''' Built on top of Clang’s frontend infrastructure for full compatibility with standard C/C++ codebases.
* '''Minimal Intrusiveness''' Generates valid, syntactically correct C/C++ code that can be:
** Output as a separate file, or
** Directly appended to the end of the processed C/C++ source file.
* '''Inline Stub Insertion''' In a common usage scenario, the stub code is inserted '''at the end of the original .cpp file''', keeping everything in one translation unit. This avoids changes to build configurations and simplifies testing or integration.
* '''Aggregate Initialization''' Aggregate types are initialized with brace-enclosed initializer lists.
* '''Selective Stubbing''' Users can control symbol exclusion via opt-out list
* '''Configuration''' YAML config for advanced scenarios and per-file options

== Use Cases ==

* '''Isolated Unit Testing''' During unit testing, individual classes or functions are compiled without all dependent files. By appending stubs to the test target file, developers can:
** Compile isolated .cpp files
** Avoid linker errors due to missing symbols
** Easily test legacy code with unknown or complex dependencies
* '''Static performance analysis''' on partial codebases.
* '''Early integration''' of modules before all dependencies are available.
* '''CI/CD build stability''' even with missing components.
* '''C/C++ to other language migration''' workflows (e.g., Rust), where linkability is required before full conversion.

== Example ==

The following table shows examples of output generated by the link stubber. To simplify the examples, the main function is omitted. The tool can optionally generate a `main` function if missing.

{| class="wikitable"
|+ Example: Stub generation
!Input C++ Source
!Generated Stubs
|-
|valign="top"|<syntaxhighlight lang="c++">
extern int var1;

namespace ns {
extern int var2;
}

void func() {
var1 = 0;
ns::var2 = 1;
}
</syntaxhighlight>
|valign="top"|Demonstrates the generation of global variables across namespaces.
<syntaxhighlight lang="c++">
int ns::var2 = (int)0;

int var1 = (int)0;
</syntaxhighlight>
|-
|valign="top"|<syntaxhighlight lang="c++">
struct B1 {
B1(int i);
int i;
};

struct S1 : public B1 {
S1(int j);
int j;
};

extern S1 var1;

void func() {
var1.i = 1;
var1.j = 1;
}
</syntaxhighlight>
|valign="top"|Shows constructor stubbing with inheritance and initialization of extern objects.
<syntaxhighlight lang="c++">
B1::B1(int i) {
}

int __tmp1 = (int)0;

S1::S1(int j) : B1(__tmp1) {
}

int __tmp0 = (int)0;

S1 var1(__tmp0);
</syntaxhighlight>
|-
|valign="top"|<syntaxhighlight lang="c++">
class C {
public:
static void func2();
int func3();
};

void func() {
C::func2();
C().func3();
}
</syntaxhighlight>
|valign="top"|Handles stub generation for static and non-static member functions.
<syntaxhighlight lang="c++">
int __tmp0 = (int)0;

int C::func3() {
return __tmp0;
}

void C::func2() {
}
</syntaxhighlight>
|-
|valign="top"|<syntaxhighlight lang="c++">
class V1 {
public:
V1();
virtual ~V1();
virtual void test() = 0;
};

class C1 : public V1 {
public:
C1();
void test();
};

extern C1 var1;

void func() {
var1.test();
}
</syntaxhighlight>
|valign="top"|Demonstrates stub generation for abstract base classes and virtual methods.
<syntaxhighlight lang="c++">
V1::V1() {
}

C1::C1() : V1() {
}

V1::~V1() noexcept {
}

C1 var1;

void C1::test() {
}
</syntaxhighlight>
|-
|valign="top"|<syntaxhighlight lang="c++">
#include <vector>

extern std::vector<int> var1;

int func1() {
return var1.size();
}
</syntaxhighlight>
|valign="top"|Handles standard library containers such as std::vector.
<syntaxhighlight lang="c++">
std::vector<int, std::allocator<int>> var1;
</syntaxhighlight>
|}

== Limitations ==

* Stub implementations are not functional — they only satisfy the linker.
* Care must be taken to avoid executing stubbed functions in functional tests.
* Test engineers can use the generated stubs as templates and extend them with realistic behavior if needed.

== Interested? ==
{{CallToAction|text=Interested in applying this coverage workflow to your own projects?}}

[[Category:emmtrix Tools]]

emmtrix Code Generator

2025-09-04T08:14:53Z

Mira.steinmetz: /* Interested? */

[[File:emmtrix Code Generator Icon.png|frameless|150x150px]]

== Our Solution for MATLAB® Code Generation ==
emmtrix Code Generator (eCG) translated MATLAB®, GNU Octave, or Scilab code into platform-independent and readable C or C++ code suitable for embedded processors. The generated code was easy to understand, prepared for parallelization, and could be adjusted to individual requirements. Automatically generated reports helped with the code certification process. In combination with [https://www.emmtrix.com/tools/emmtrix-parallel-studio emmtrix Parallel Studio], eCG enabled multicore programming or vectorization directly from *.m or *.sci script files. Furthermore, eCG worked hand in hand with [[emmtrix Model Code Generator]] to support C code generation from Simulink® models.

== eCG Workflow ==
[[File:emmtrix Code Generator Workflow.png|frameless|600x600px]]

emmtrix Code Generator used *.m script files (MATLAB® or GNU Octave) or *.sce/sci script files (Scilab) as input and generated sequential C code according to C89, C99, or C11 standards as output. All generated source and header files could be directly compiled without dependencies on external libraries. A direct generation of executable files was also possible. When fixed-point data types were used, C++ templates were employed to represent them.

The generated C code was static and free of dynamic memory allocation, making it suitable for embedded systems and for parallelization tools like [https://www.emmtrix.com/tools/emmtrix-parallel-studio emmtrix Parallel Studio]. Data dependencies could easily be analyzed. Matrices were represented by multi-dimensional arrays to enable loop transformations required for parallelization or vectorization.

Users could extend their input scripts with special eCG directives (similar to pragmas in C). These directives were treated as comments by the original tools, ensuring code compatibility. The special directives could be used to provide additional information in the output code, select different algorithms for built-in functions like FFT, or enable various code optimizations to improve performance, memory consumption, or parallelizability.

== Features ==

* Supported code generation compliant with ISO C90, C99, C11, C18, C++98, C++11, C++14, and C++17 standards
* Performance & memory analysis
* Highly comprehensive target-optimized C/C++ code
* User-controlled cache and memory optimization
* Bidirectional traceability via code generation reports
* Embedded code generation without dynamic memory allocation

* Interfacing custom C/C++ code or libraries
* Automatable back-to-back tests for functional validation
* Usable within continuous integration processes
* Automatic floating-point to integer number conversion
* Profiling-based performance analysis and visualization within GUI
* Worst-case analysis
* Optional array bound checking within generated code

== Supported MATLAB®/GNU Octave/Scilab Language Features ==

* N-dimensional arrays
* Matrix operations
* Processing of multiple input files
* Variable-sized variables (growing arrays)
* Subscripting, linear and logical indexing
* Double-precision, single-precision, and integer data types

* Complex numbers
* Fixed-point arithmetic
* Program control statements if, for, while, break, continue and switch/case
* Arithmetic, relational, and logical operators
* Function handles

* Structures and array of structures
* Global variables
* Recursive function calls
* Global and local functions
* Functions with variable-length input/output arguments
* Over 100 MATLAB®/GNU Octave/Scilab functions supported

== emmtrix Code Generator Online - still available ==
Try out [https://www.emmtrix.com/online-emmtrix-code-generator/ emmtrix Code Generator Online]. This version of eCG allows easy conversion of MATLAB® or Scilab scripts to C code. Upload your script files directly or type the code into the editor window and convert the code with a single click of a button.

It offers the following features: generation of HTML reports with lots of information of the automated analysis, access to the latest versions of eCG, use the generated C code without any additional runtime environment or framework, generates all files required for compilation: C sources and headers including utility functions as well as a Makefile.

Go to eCG Online: https://www.emmtrix.com/online-emmtrix-code-generator/

emmtrix Code Generator

2025-09-04T08:13:59Z

Mira.steinmetz:

emmtrix C++ to C Compiler

2025-09-04T08:12:43Z

Mira.steinmetz:

[https://www.emmtrix.com/tools/emmtrix-cpp-to-c-compiler emmtrix C++ to C Compiler (eCPP2C)] automatically translates your C++ source code into analyzable C code. The design goal was to keep the binary compilation of the original C++ code and the binary compilation of the translated C code mostly identical. This guarantees the functional correctness of the generated C code. [https://www.emmtrix.com/tools/emmtrix-cpp-to-c-compiler eCPP2C] utilizes the LLVM/Clang compiler technology to enable support of the latest features of the fast evolving C++ standard. In combination with [https://www.emmtrix.com/tools/emmtrix-parallel-studio emmtrix Parallel Studio], [https://www.emmtrix.com/tools/emmtrix-cpp-to-c-compiler eCPP2C] enables software parallelization of C++ applications.

== Features ==

* Translation of C++ to C11 (ISO/IEC 9899:2011) source code
* Utilizes latest LLVM/Clang compiler technology
* Gurantees functional correctness of generated C code by verification tool
* eCPP2C Qualification Kit (ISO 26262, DO-178C/330 or any comparable standard) can be provided on request
* Demystifies how your C++ code is compiled to assembler
* Can be used in combination with (certified) C compilers and C code analysis tools
* Integrated into emmtrix Parallel Studio GUI to enable C++ code parallelization

== Supported C++ Language Features ==
The following list displays some of the C++ language features supported by the C++ to C Compiler:

* Classes
* Multiple inheritance
* New/Delete
* Namespaces
* extern “C”
* Using
* Friends
* Lambda expressions

* Static assert
* C++ casts
* Auto
* References
* Rvalue references
* Move semantic
* Range-based for loops
* STL containers

* Templates
* Variadic Templates
* Copy elision
* Trailing return types
* User-defined literals
* C++11-style attributes
* Scoped enums
* …

[https://www.emmtrix.com/tools/emmtrix-cpp-to-c-compiler emmtrix C++ to C Compiler] is under active development and it aims to support the full feature set of the C++17 (ISO/IEC 14882:2017) standard as well as common GCC / Clang language extensions.

Interested in having C++ exceptions supported? Even though this C++ feature does not have an equivalent we can provide a solution to you upon request (see contact details at the buttom of the page).

== Verification Tool and Test Strategy ==
[https://www.emmtrix.com/tools/emmtrix-cpp-to-c-compiler emmtrix C++ to C compiler] has a unique verification and testing strategy that guarantees that the generated C code is semantically equivalent to C++.
* See [[C++ to C Test Strategy]]

== emmtrix C++ to C Compiler Online ==

Try out emmtrix [https://online-ecpp2c.emmtrix.com/ C++ to C Compiler Online] powered by [https://godbolt.org/ Compiler Explorer]. We have integrated our tool [https://www.emmtrix.com/tools/emmtrix-cpp-to-c-compiler eCPP2C] into the Compiler Explorer framework so that you can enter your C++ code and immediately see the converted C code.

== See Also ==
* [[Demystifying C++]] - Demystifying C++ article series based on the output of the tool
* Office webpage at https://www.emmtrix.com/tools/emmtrix-cpp-to-c-compiler

== Interested? ==
{{CallToAction|text=Interested in applying this coverage workflow to your own projects?}}

[[Category:C++ to C Compiler]]

emmtrix Code Vectorizer

2025-09-04T08:12:16Z

Mira.steinmetz:

emmtrix Code Vectorizer is a C source-to-source compiler that vectorizes C code for various SIMD architectures like [[Infineon AURIX TC4x|Infineon AURIX TC4x PPU]], x86 AVX, ARM NEON, or RISC-V V extensions. It follows an semi-automatic approach, where the user can guide the vectorization process from an Eclipse-based GUI or by using pragmas in the C code. The vectorized C code is always visible to the user, which makes it easy to follow the transformation and to understand the generated code. The generated code can be compiled with the vendor’s compiler and either run on the target hardware or in a simulator to get performance feedback and verify the correctness of the transformation.

=== Multi-Precision Vector Math Library ===
The emmtrix Code Vectorizer incorporates a multi-precision vector math library that provides vectorized implementations of common C mathematical functions like sinf, cosf, expf, logf, powf, sqrtf, tanhf and many more. The library provides multiple versions of each function to provide the best trade-off between accuracy and performance. During vectorization, the vector math library is used to replace scalar math functions with vectorized versions. By specifying the accuracy requirements in [[ULP Difference of Float Numbers|ULPs (units in the last place)]], the user can control which version of the function is used.
{| class="wikitable"
|-
! Function
!Info
! Accuracy<ref>Accuracy of hardware version are given from the data sheet. A ULP 0.0 means that the implementation is exact. Otherwise, the highest know ULP is provided. Math functions that are based on non-perfect hardware implementation use a pessimistic software implementation for ULP evaluation. A more accurate ULP evaluation could be provided on request.</ref> [ULP]
! Latency on AURIX™ TC4x [cycles]
! Throughput on AURIX™ TC4x [cycles]
|-
|fabsf
|
|0.0
|
|
|-
|fminf
|
|0.0
|
|
|-
|fmaxf
|
|0.0
|
|
|-
|roundf
|
|0.0
|11
|5
|-
|ceilf
|
|0.0
|6
|4
|-
|floorf
|
|0.0
|6
|4
|-
|truncf
|
|0.0
|6
|4
|-
| sqrtf
|Hardware version
| 0.5
|16
|7
|-
| expf
|Hardware version
| 1.0
|11
|6
|-
|exp2f
|Hardware version
|1.0
|14
|6
|-
| log2f
|Hardware version
| 1.0
|14
|6
|-
|logf
|Based on log2f ULP 1.0 hardware version
|1.93
|
|
|-
|log10f
|Based on log2f ULP 1.0 hardware version
|2.50
|
|
|-
| sinf
|Hardware version
| 1.0
|14
|6
|-
| cosf
|Hardware version
| 1.0
|14
|6
|-
|tanf
|Based on sinf/cosf ULP 1.0 hardware version
|3.42
|
|
|-
| rowspan="4" | tanhf
| rowspan="4" |Based on expf ULP 1.0 hardware version
|7.08
|41
|18
|-
|4.23
|41
|19
|-
|2.74
|41
|23
|-
|1.91
|41
|27
|-
|hypotf
|Based on sqrt ULP 0.5 hardware vesrion
|1.995
|
|
|-
|remainderf
|
|
|
|
|-
|fmodf
|
|
|
|
|-
|fdimf
|
|
|
|
|}

[[Category:emmtrix Tools]]
<references />

== Interested? ==
{{CallToAction|text=Interested in applying this coverage workflow to your own projects?}}
[[Category:Math Function Accuracy]]

emmtrix Performance Estimator

2025-09-04T08:10:17Z

Mira.steinmetz:

[https://www.emmtrix.com/tools/emmtrix-performance-estimator emmtrix Performance Estimator (ePE)] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / [https://emmtrix.com/wiki/Infineon_AURIX_TC3xx TC3xx]/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

=== Estimation Methods ===
In general, the execution time of a task or block can be modelled as:

''texec = execution_frequencyblock* single_durationblock''

The C code based static code analysis derives the execution frequency by analyzing loop boundaries using constant folding. For the duration, each instruction in the code is modeled as the number of cycles of an abstract hardware model of the processor, and then summed.

ePE offers three accuracy levels:
*analysis of C code
*generically compiler-optimized code
*assembly code from the target compiler.
Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

==== Static Code Analysis: ====
[[File:Static Code Analysis.jpg|frameless|800x800px]]

==== Processor Pipeline: ====
[[File:ePE Processor Pipeline.png|frameless|950x950px]]

[https://www.emmtrix.com/tools/emmtrix-performance-estimator emmtrix Performance Estimator (ePE)] supports different ways to acquire the duration of the tasks of an application. These methods vary in accuracy and additional software or hardware requirements. Static code analysis provides basic information without the need for hardware or special software and may thus be seamlessly incorporated into early stages of the Software Development Life Cycle (SDLC). More accurate numbers can be collected with interfaces to simulators or the hardware. Depending on the requirements, the methods can be combined as desired.

Addressing performance issues at the onset of the SDLC is not only proactive but also cost-efficient. Early estimation and intervention, as suggested by the below graph, can drastically reduce the complexities and expenses associated with fixing defects post-deployment. Although early estimates may not be as precise as measurements taken during later stages, they serve as a crucial checkpoint to prevent potential timing issues from escalating. This preemptive approach aligns with the principle that the cost to repair defects increases exponentially as they progress through the SDLC, as shown by the sharp rise in cost depicted in the graph. Hence, initial performance estimations are a strategic investment, minimizing the risk of facing a steep climb in remediation costs and efforts at later stages.
[[File:DefectDetectionandRemediation.webp|center|frameless|800x800px|Cost of Defect Remediation across the Software Development Life Cycle]]

== Interested? ==
{{CallToAction|text=Interested in applying this coverage workflow to your own projects?}}
[[Category:emmtrix Tools]]

emmtrix Dependency Analyzer

2025-09-04T08:09:14Z

Mira.steinmetz:

[https://www.emmtrix.com/tools/emmtrix-dependency-analyzer emmtrix Dependency Analyzer (eDA)] analyzes C source code to extract which output signals/variables depend on which input signals/variables.

== Dependency Analysis ==
The core dependency analysis of [https://www.emmtrix.com/tools/emmtrix-dependency-analyzer eDA] tool is using the C source code and an entry function (typically a runnable in an automotive application) as input. It calculates which global variables depend on each other when the function is executed. If a variable v1 depends on variable v2, the result of v1 (after function execution) is somehow influenced by the value of v2 (before function execution) when the function is executed.

The dependency analysis is not limited to programs using global variables for transporting information. By applying an automatic preprocessing and postprocessing step, more generic programs can be transformed into programs using global variables. This way we can e.g. detect dependencies between AUTOSAR signals, network communication function, etc.

=== Simple Case ===

In the following example, we have the global variables <code>in1</code>, <code>out1</code>, <code>out2</code> and <code>out3</code>.

* <code>in1</code> is assigned to out1, so the value of <code>out1</code> depend on <code>in1</code>.
* <code>in1</code> is not changed in the function, so it is not listed in the results.
* <code>out2</code> is assigned a constant value, so it has no dependency on any input value.
* <code>in1</code> is added to <code>out3</code>, so the value of <code>out3</code> depends both on <code>in1</code> and on <code>out3</code> itself (i.e. the value prior function execution).

{| class="wikitable"
|+
!Input Code
!Result
|-
|
<syntaxhighlight lang="c">
int in1;
int out1, out2, out3;

void func(void) {
out1 = in1;
out2 = 5;
out3 += in1;
}
</syntaxhighlight>
|<pre>out1: in1
out2: -
out3: out3 in1
</pre>
|}

=== Conditional ===

[https://www.emmtrix.com/tools/emmtrix-dependency-analyzer eDA] distinguish between two kinds of dependencies:

# '''Data dependencies''' are caused by assigning a value to variable.
# '''Control dependencies''' are caused by the control structure of the program e.g. if a variable changed conditionally. Control dependencies are indicated in the results by the <code>(c)</code> suffix.
[https://www.emmtrix.com/tools/emmtrix-dependency-analyzer eDA] restricts that one variable can be either control or data dependent on another variable. The data dependency is considered stronger that the control dependency. If both dependencies appear, only the data dependency will appear in the results.

In this example, the dependency of output variables on input variables is determined based on a conditional if statement. The function checks the value of in1 to decide which values to assign to out1 and out2. The result shows that out1 is control dependent on in1 and data dependent on in2. out2 is both control and data dependent on in1 but only the dominant data dependency is shown.

{| class="wikitable"
|+
!Input Code
!Result
|-
|
<syntaxhighlight lang="c">
int in1, in2;
int out1, out2;

void func(void) {
if (in1) {
out1 = in2;
out2 = in1;
} else {
out1 = 0;
out2 = 0;
}
}
</syntaxhighlight>
|<pre>out1: in1(c) in2
out2: in1
</pre>
|}

=== Delay Elements ===
In this example, a simple implementation of a delay element is shown. The output variable out1 is assigned the value of in1 from the previous function call. If the function is executed only one time, the output variable is not influenced by any input variable and thus would only have a dependency to the internal variable.

[https://www.emmtrix.com/tools/emmtrix-dependency-analyzer eDA] considers this scenario by calculating the dependencies for multiple function calls. If one variable is dependent on a variable from a previous function call, it is considered as a delayed (data or control) dependency. Delayed dependencies are indicated in the results by a suffix of <code>^-N</code>, where N is the number of function calls the dependency is delayed. Internally non-delayed dependencies are modeled as delayed dependencies with N=0. One variable cannot have multiple delayed or non-delayed dependencies to the same variable. Dependencies with a smaller delay are considered stronger than dependencies with a larger delay.
{| class="wikitable"
|+
!Input Code
!Result
|-
|
<syntaxhighlight lang="c">
int in1;
int out1;
static int internal1;

void func(void) {
out1 = internal1;

internal1 = in1;
}
</syntaxhighlight>
|<pre>internal1: in1
out1: internal1 in1^-1
</pre>
|}

=== Local Variables ===
In this example, two local variables are used to store intermediate results. eDA considers the local variables and their dependencies to the global variables. The result shows that the output variable out1 is dependent on in1 and in2. The local variables are not listed in the results as their lifetime ends after the function execution.
{| class="wikitable"
|+
!Input Code
!Result
|-
|
<syntaxhighlight lang="c">
float in1, in2;
float out1;

void func(void) {
float local1;
float local2;

local1 = in1 * in1 + in2 * in2;
local2 = sqrt(local1);

out1 = local2 + 1.0f;
}
</syntaxhighlight>
|<pre>out1: in1 in2
</pre>
|}
=== Ignoring Name Dependencies===
In this example, the local variable local1 is reused to store two different intermediate results. Reusing (global or local) variables is common in C programming and also used by code generators like TargedLink. A name-based dependency analysis would consider the output variable out2 dependent on in1 and in2. However, [https://www.emmtrix.com/tools/emmtrix-dependency-analyzer eDA] ignores the name of the variable and considers only the data flow. The result shows that out2 is only dependent on in2.
{| class="wikitable"
|+
!Input Code
!Result
|-
|<syntaxhighlight lang="c">
float in1, in2;
float out1, out2;

void func(void) {
float local1;

local1 = in1 * in1;
out1 = local1;

local1 = sqrt(in2);
out2 = local1;
}
</syntaxhighlight>
|<pre>out1: in1
out2: in2
</pre>
|}

Ignoring name dependencies is especially important for TargetLink-generated code. TargetLink uses `AUX_*` variables that are reused for different intermediate results. Name dependencies would lead to many false dependencies and thus to many false positives. In one relevant use case, the number of dependencies was reduced by 90% by ignoring name dependencies.

=== Arrays ===

In this example, an array A is used to store the input variables in1 and in2. The results show that the array variable A is dependent on in1 and in2. However, eDA considers the array elements as separate variables if they are accessed by constant indices. The output variable out1 is only dependent on in1.

{| class="wikitable"
!Input Code
!Result
|-
|<syntaxhighlight lang="c">
int in1, in2;
int A[10];
int out1;

void func(void) {
A[0] = in1;
A[1] = in2;

out1 = A[0];
}
</syntaxhighlight>
|<pre>A: in1 in2
out1: in1
</pre>
|}

=== Function Calls ===

In this example, the function add is used to calculate the sum of two input variables. The function is called 3 times with different arguments. [https://www.emmtrix.com/tools/emmtrix-dependency-analyzer eDA] not only considers the data dependencies between the parameters and the return value but also calculates the dependencies for each call separately. The result shows that out1 is dependent on in1 and in2, out2 is dependent on in1 and out3 is independent of any input variable.

{| class="wikitable"
!Input Code
!Result
|-
|<syntaxhighlight lang="c">
int in1, in2;
int out1, out2, out3;

int add(int a, int b) {
return a + b;
}

void func(void) {
out1 = add(in1, in2);
out2 = add(in1, 1);
out3 = add(5, 6);
}
</syntaxhighlight>
|<pre>out1: in1 in2
out2: in1
out3: -
</pre>
|}

=== Call by Reference Function Parameters ===

In this example, the function swap uses pointers to swap the values of two input variables. ...

{| class="wikitable"
!Input Code
!Result
|-
|<syntaxhighlight lang="c">
int in1, in2;
int out1, out2;

void swap(int* a, int* b) {
int c = *a;
*a = *b;
*b = c;
}

void func(void) {
out1 = in1;
out2 = in2;

swap(&out1, &out2);
swap(&out1, &out2);
}
</syntaxhighlight>
|<pre>out1: in1
out2: in2
</pre>
|}

=== Parametrized Dependency Analysis===
In automotive applications, it is common to use the same software across multiple car models with different configurations. [https://www.emmtrix.com/tools/emmtrix-dependency-analyzer eDA] supports a parametrized dependency analysis where one or more input variables are considered as constant parameters. Code parts that are deactivated by the constant parameters are not considered during dependency analysis. This is useful to calculate the dependencies only for one active configuration and to reduce the number of dependencies.

[https://www.emmtrix.com/tools/emmtrix-dependency-analyzer eDA] follows a two step approach for the parametrized dependency analysis. In the first step, the constant parameters are propagated through the code and inactive code parts are removed. In the second step, the dependency analysis is performed on the transformed code. Even the transformed code is available as intermediate code for transparency reasons. This is useful to understand the results and to verify the correctness of the transformation.

The following example is identical to the conditional example. Only the input variable in1 is considered as a constant parameter (indicated by the <code>static const</code> in the input code). The result shows the intermediate code after the transformation. The if statement is removed and the output variables are assigned the values of the else branch. In contrast to the conditional example, the output variables are not dependent on the input variable in1.
{| class="wikitable"
|+
!Input Code
!Intermediate Code
!Result
|-
|<syntaxhighlight lang="c">
static const int in1 = 0;
int in2;
int out1, out2;

void func(void) {
if (in1) {
out1 = in2;
out2 = in1;
} else {
out1 = 0;
out2 = 0;
}
}
</syntaxhighlight>
|<syntaxhighlight lang="c">
int in2;
int out1, out2;

void func(void) {
out1 = 0;
out2 = 0;
}
</syntaxhighlight>
|<pre>out1: -
out2: -
</pre>
|}

=== AUTOSAR Integration ===
In AUTOSAR, ports are accessed using IRead/IWrite function. By providing dummy implementations of these functions that simple read or write a dummy global variable, the AUTOSAR program is transformed into a program with global variables. This is used as input for the dependency analysis.

=== Output Format Example ===
A small source code example is shown in the next figure. The code uses three global variables g1. g2 and g3 as well as two output variables out1 and out2. The dependency analysis extracts how the output depend on the input variables.

[[File:emmtrix_Dependency_Analyzer_input.png|alt=emmtrix Dependency Analyzer -Input|frameless|262x262px]]

The results are shown in the XML file in the next figure. Variable out1 depends on g3 and g2 whereas the dependency to g3 is a control dependency and to g2 a data dependency. Variable out2 only depends on g1.

[[File:emmtrix Depenendy Analyzer xml results.png|frameless|600x600px]]

More information can be seen as comments inside of the C code. The next figure shows all use (read) and def (write) accesses to all variables in the program. Control dependencies are marked with (c), delayed dependencies that depend on values from a previous iteration by ^-1. Phi statements are virtual instructions that are placed when the value of a variable depends on a condition. This kind of representation is useful to see the dependencies directly where they come from in the source code.

An extract from the full dependency graph can be seen in the next figure. It shows statements from the source code and how they depend on each other:

* ''SSA:'' there exists a use/def dependency where one signal writes a value and another one reads it
* ''Control:'' a control dependency caused by a condition (branch) instruction exists
* ''CallArg:'' the statement depends on an argument of the function
* ''Expr: '' the statement is part of the previous expression.

This kind of visualization can help pinpoint the root of a specific dependency.

=== Undescribed Features ===

* Function calls to known functions
* Function calls to unknown functions
* Loops
* Switch case
* Output
** C debug output
** XML output
** Reachability output
** Dependency path output
* Propagation of tags (e.g. OBD, ASIL-D)
* AUTOSAR integration
* [[Bitblast Transformation]]

== See Also ==

* Official webpage - https://www.emmtrix.com/tools/emmtrix-dependency-analyzer

== Interested? ==
{{CallToAction|text=Interested in applying this coverage workflow to your own projects?}}

[[Category:emmtrix Tools]]

Explicit Cast Insertion

2025-06-03T07:27:51Z

Mira.steinmetz: Mira.steinmetz moved page Explicit Cast Insertion to Explicit Cast Insertion Transformation

#REDIRECT [[Explicit Cast Insertion Transformation]]

Explicit Cast Insertion Transformation

2025-06-03T07:27:51Z

Mira.steinmetz: Mira.steinmetz moved page Explicit Cast Insertion to Explicit Cast Insertion Transformation

{{DISPLAYTITLE:Explicit Cast Insertion Transformation}}

Explicit cast insertion is a transformation that introduces explicit type casts in situations where implicit type conversions would otherwise occur. By making type conversions explicit, this technique improves code clarity, prevents unintended behavior, and enhances static code analysis. It is particularly useful in strongly typed languages, ensuring that conversions are intentional and reducing ambiguity in expressions involving mixed data types. While preserving program semantics, explicit cast insertion helps avoid compiler warnings and improves maintainability by making type changes more transparent.
==Explicit Cast Insertion Transformation in emmtrix Studio==
emmtrix Studio can implement explicit cast insertion using #pragma directives or via the GUI. Cast insertion is a transformation that inserts explicit type casts in situations where implicit type conversion will take place. The transformation preserves the code-semantics.
===Typical Usage and Benefits===
The transformation is used to generate clearer code and to increase capabilities of the code analysis.
===Example===
{| class="wikitable"
|-
| <syntaxhighlight lang="c">
/* The following code tests cast insertion transformation applied to main function.
* In the given example, in expressions sum(a, b), if (a) and x ? a : b, there is implicit type conversion.
* Explicit type casts are inserted in the relevant places.
*/

int sum(int num1, int num2) {
return num1 + num2;
}
#pragma EMX_TRANSFORMATION ExplicitCastInserter
int main(void) {
char a = 5;
char x = 's';
float b = 3.14159;
int c;
sum(a, b);
if (a) {
printf(” % c\ n”, a);
}
c = x ? a : b;
return 0;
}
</syntaxhighlight>
|<syntaxhighlight lang="c">
/* The following code is the generated code after the transformation has been applied.
*/

int sum(int num1, int num2) {
return num1 + num2;
}
int main() {
char a = (char) 5;
char x = (char)
's';
float b = (float) 3.14159;
int c;
sum((int) a, (int) b);
if ((_Bool) a) {
printf(” % c\ n”, a);
}
c = (int)((_Bool) x ? (float) a : b);
return 0;
}
</syntaxhighlight>
|}
[[Category:Code Transformation]]

Infineon AURIX TC4x

2025-05-21T08:19:22Z

Mira.steinmetz:

[[File:Infineon Aurix TC4x.webp|right|frameless]]
The TC4x is Infineon's latest generation of AURIX™ microcontrollers, designed for advanced automotive applications, including eMobility, Advanced Driver Assistance Systems (ADAS), and automotive E/E (Electric/Electronic) architectures. These microcontrollers are built on a 28 nm process and feature the [[TriCore Instruction Set Architecture|TriCore™ 1.8 instruction set architecture]], which includes up to six cores running at speeds up to 500 MHz. This architecture is optimized for high-performance and real-time applications.

== Key Features ==
* '''High Performance and Scalability''': Equipped with a Parallel Processing Unit (PPU), Data Routing Engine (DRE), and other accelerators to enhance AI capabilities and real-time processing.
* '''Extensive Connectivity''': Supports high-speed communication interfaces such as 5 Gbps Ethernet, PCIe, CAN-XL, and 10BASE-T1S Ethernet, providing flexibility and performance for various automotive applications.
* '''Enhanced Security''': Compliant with ISO 21434, the TC4x includes advanced cybersecurity modules and supports safe, over-the-air (SOTA) updates with zero downtime.
* '''Memory and Storage''': Features up to 25 MB of on-chip flash memory, allowing for complex software applications and data storage.
* '''Real-Time Control''': Advanced timers and ADCs (Analog-to-Digital Converters) improve control loops for electric motors and power conversion tasks.

== Architecture ==
[[File:Infineon TC4x Architecture.png|thumb|Infineon TC4x architecture|494x494px]]

=== System Architecture ===

=== TC 1.8P Processor Core (CPU0 ... CPU5) ===

=== Parallel Processing Unit (PPU) ===
The PPU is an implementation of the '''DesignWare ARC EV71 Processor'''. The length of the vector registers is flexible and depends on the version. Commercially, 128 or 256 bit vector registers are available. In a pre-series stepping even 512 bit was used.

See [[Infineon AURIX TC4x Parallel Processing Unit (PPU)]]

== Applications ==
* eMobility
* ADAS
* Automotive E/E architectures
* Affordable artificial intelligence (AI) applications

== emmtrix Tools for AURIX™ TC4x ==
emmtrix offers several tools for the Infineon AURIX™ TC4x architecture:

* [https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer] for vectorizing C code for the Infineon PPU. emmtrix was working together with Infineon already during develop of the TC4x architecture for supporting the PPU and received one of the first series A test boards.
* [https://www.emmtrix.com/tools/emmtrix-performance-estimatorator emmtrix Performance Estimator] for estimating the performance of C code written for the Tricore™ CPUs.

[[File:Infineon Board.png|thumb|Infineon Development Board (AURIX™ TC4x Communication Board)]]

=== emmtrix Code Vectorizer ===
[https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer (eCV)] simplifies programming the Parallel Processing Unit (PPU) on Infineon’s '''AURIX™ TC4x microcontrollers''', enabling significant acceleration of data-parallel applications like sensor fusion or AI inference. By leveraging the PPU, these tasks can be accelerated by factors >10, unlocking the full potential of hardware capabilities.

eCV automates the vectorization process, transforming sequential C code into optimized vectorized code tailored to the '''AURIX™ TC4x architecture'''. This includes efficient handling of memory layouts and advanced loop transformations. Developers can simulate and test functionality even without access to target hardware, reducing development time and effort.

With support for '''Simulink® models, ONNX-based AI workflows,''' and detailed performance insights through integrated simulators, eCV minimizes the need for manual optimization while maximizing hardware performance.[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.]]

=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / [[Infineon AURIX TC3xx|TC3xx]] / TC4x microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===
====Architecture & Variant Consulting====
*Support in selecting suitable AURIX derivatives for new product generations (trade-offs between performance, price, safety, and peripheral features)
*Analysis of requirements and mapping to specific AURIX product families (e.g., TC3xx vs. TC4xx)
*Analysis/identification of performance margins for down- or upgrades
====Runtime Analysis & Performance Engineering====
*Execution of detailed runtime analyses (maximum/minimum vs. average)
*Identification of bottlenecks in program execution, including benchmarking
*Optimization of access to flash, RAM, and peripherals (e.g., cache configuration, DMA utilization)
====Dependency Analysis====
*Freedom from interference (ASIL level check)
====Multicore Design & Scheduling Concepts====
*Development of core mapping strategies (static vs. dynamic assignment of compute-intensive tasks)
*Support for integrating bare-metal scheduling on AURIX
*Assistance with architectural decisions to meet functional safety requirements in multicore systems

==== PPU Vector Accelerator ====

* Acceleration of existing projects or migration of components to the PPU

* Support for new projects (selection of suitable components for acceleration), assistance with vectorization
* Debugging of vectorized code

====Training & Know-how Transfer====
*Technical in-house workshops on AURIX optimization, multicore strategies
*Coaching of employees/project teams in performance analysis and systematic tuning
== See Also ==

* [[Infineon AURIX TC4x Parallel Processing Unit (PPU)]]
* [[Infineon AURIX TC3xx]]
* [[TriCore Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc4x/

[[Category:Supported Architectures]]

Infineon AURIX TC3xx

2025-05-21T08:17:16Z

Mira.steinmetz:

[[File:AURIX TC399 LFBGA-516 plain.jpg|thumb|Infineon AURIX™ TC3xx second-generation microcontroller (TC399 BGA package). The AURIX™ TC3xx family integrates multiple TriCore™ CPUs and on-chip safety/security modules for automotive applications.|alt=TC399 BGA package]]
The '''Infineon AURIX™ TC3xx''' (Automotive Realtime Integrated neXt-generation architecture) is a family of 32-bit automotive microcontrollers introduced as the second generation of Infineon’s AURIX™ platform. Launched in 2016 as a successor to the earlier [[Infineon AURIX TC2xx|AURIX™ TC2xx series]], the TC3xx devices emphasize high performance, functional safety, and embedded security for advanced automotive and industrial applications. AURIX™ TC3xx microcontrollers feature a hexa-core [[TriCore Instruction Set Architecture|''TriCore'' processor architecture]] with enhanced safety measures, making them well-suited for demanding tasks such as autonomous driving domain controllers, powertrain control, and sensor data fusion in advanced driver-assistance systems (ADAS). The combination of multiple CPU cores, extensive on-chip memory, and a rich peripheral set allows TC3xx chips to deliver real-time responsiveness and reliability in safety-critical environments while meeting stringent automotive standards (such as ISO 26262 for functional safety).<ref name="ref1951907555">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref><ref name="ref1428109010">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref1948477695">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
==Applications==
AURIX™ TC3xx microcontrollers are used in a variety of safety-critical and high-performance applications across the automotive and industrial sectors. Key application domains include:
*'''Automotive Systems:''' The TC3xx family was primarily designed for automotive use and finds broad application in vehicles’ electronic control units (ECUs). Notably, it is used in ''powertrain and drivetrain control'' (engine management, transmission control, hybrid/electric vehicle inverter control, battery management) where its real-time processing and resilience support precise actuator control. It is also deployed in ''chassis and safety systems'' such as anti-lock braking systems (ABS), electronic stability control, airbag controllers, and electric power steering, leveraging its redundancy and fast response for fail-safe operation. With the growth of ADAS and autonomous driving, AURIX™ TC3xx devices serve as domain controllers for ''ADAS sensor fusion'', handling data from radar, LiDAR, camera, and ultrasonic sensors and performing environment modeling and decision-making algorithms. Their combination of multiple cores and a built-in radar signal processing sub-system makes them an attractive choice for tasks like front radar processing, sensor fusion hubs, and ''autonomous driving domain controllers'' that must meet ASIL-D safety levels.<ref name="ref14281090102">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
*'''Industrial Automation and Robotics:''' Infineon has also positioned the AURIX™ family for use in industrial applications that demand high reliability. The TC3xx MCUs, with their hardware self-test mechanisms and safety documentation, can be found in ''industrial motor drives, robotics controllers, and PLCs (programmable logic controllers)'', where they help achieve functional safety certifications up to SIL-3 (according to IEC 61508). The powerful TriCore™ cores and rich peripheral set enable complex motor control algorithms (e.g., field-oriented control for servo motors) and real-time sensor processing in factory automation. Additionally, the support for automotive-grade networking (CAN/CAN-FD, Ethernet) and timing peripherals makes them suitable for synchronous control in robotics and machinery. Infineon’s provision of AUTOSAR-compatible software for AURIX™ has even facilitated its use in non-automotive settings such as medical devices and elevator controllers, where proven safety and security are required.<ref name="ref496771205">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref>
*'''Aerospace and Defense:''' The high fault-tolerance and deterministic performance of the AURIX™ TC3xx architecture also attract interest for aerospace and other mission-critical uses. In avionics systems or autonomous drones, for instance, the lockstep core configuration and robust error checking of AURIX™ can provide an added layer of reliability for flight control computers or navigation systems. While primarily an automotive chip, its ability to operate in harsh conditions (−40°C to 150°C range) and to detect internal failures in real-time makes it viable for certain aerospace electronic systems. Some defense and aerospace projects leverage COTS (commercial off-the-shelf) automotive components like AURIX™ for applications such as unmanned vehicle control and high-reliability communication links, given its safety pedigree. (In these domains, additional analysis and possibly radiation testing would be performed if the devices are used in high-altitude or space environments.)
== Architecture Overview ==
[[File:Infineon TC3xx Architecture.webp|545x545px|thumb|alt=TC3xx Architecture Overview|TC3xx Architecture Overview]]
=== Processor Cores and Architecture===
The AURIX™ TC3xx family implements Infineon’s TriCore™ architecture, which uniquely combines aspects of RISC microcontrollers, DSP (digital signal processor) capabilities, and conventional microprocessor features into a single core design. Each TC3xx device can include up to six independent TriCore™ 32-bit CPU cores (TriCore™ version 1.6.2), all capable of running at up to 300 MHz clock frequency. Four of these cores can operate in dual-core lockstep pairs (with one core acting as a redundant checker for its partner) to provide fault detection for safety-critical functions. The TriCore™ cores use a superscalar Harvard architecture with 32-bit instruction words (and support for mixed 16/32-bit instruction encoding for code density). Each core includes a dedicated Floating Point Unit (FPU) for single-precision arithmetic and supports DSP-oriented instructions (e.g. single-cycle 16×16 MAC operations, SIMD for 16-bit/8-bit data) to accelerate signal processing tasks. For fast real-time performance, the architecture offers low interrupt latency (with automatic context save on-chip) and features like zero-overhead loops and a programmable peripheral timer unit for scheduling tasks. In total, a high-end TC3xx (such as the TC39x) provides six 300 MHz cores plus four checker cores, yielding a theoretical processing throughput of up to ~2400 DMIPS (Dhrystone MIPS) when all cores are utilized. This represents roughly a threefold increase in computational power over the previous AURIX™ generation (which achieved ~740 DMIPS with three cores).<ref name="ref19484776952">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref><ref name="ref2022357806">UDE Debug, Trace and Test solutions for Infineon TriCore™ AURIX™ TC32, TC33, TC35, TC36, TC37, TC38, TC39, TC3x Microcontrollers https://www.pls-mc.com/products/infineon-tricore-aurix-tc32-tc33-tc35-tc36-tc37-tc38-tc39-microcontrollers/</ref><ref name="ref14281090103">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref>
===Memory Subsystem and Cache===
AURIX™ TC3xx microcontrollers integrate a large on-chip memory system to meet real-time and safety requirements. Program flash memory sizes range up to 16 MB on the largest models, with over 6 MB of on-chip SRAM available for data and scratchpad usage. Each TriCore™ CPU has its own tightly-coupled local memories as well as caches: for example, each core includes a 32 KB instruction cache and a 16 KB data cache. In addition, every core has separate local RAM blocks (Harvard architecture) for instructions and data (often termed PSPR and DSPR – Program Scratch-Pad RAM and Data Scratch-Pad RAM) that allow deterministic access for time-critical routines. Shared global memory is provided via a Local Memory Unit (LMU) which can be up to several hundred kilobytes (for instance, 768 KB in the TC39x) accessible by all cores. The memory system is connected by a high-bandwidth internal bus fabric (the SRI crossbar and peripheral buses) that arbitrates access between cores, DMA engines, and peripherals. This architecture ensures that each core can quickly fetch instructions and data either from its local cache/RAM or the central memory, enabling efficient parallel processing. Memory protection hardware is also built-in to isolate tasks of different criticality, an important feature for safety and security.<ref name="ref19484776952" /><ref name="ref5727814512">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
===Peripherals and Interfaces===
One of the strengths of the AURIX™ TC3xx architecture is its extensive set of on-chip peripherals and interface controllers, designed to handle the complex networking and I/O needs of modern vehicles and industrial systems. Key peripheral features and interfaces include:<ref name="ref19484776952" /><ref name="ref2022357806" /><ref name="ref14281090103" /><ref name="ref3635926">AURIX™ Training System Architecture https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_System_Architecture-Training-v01_00-EN.pdf?fileId=5546d46272e49d2a0172eb476d56739e</ref>

* '''Networking Interfaces:''' Multiple CAN FD controllers (supporting up to 12 CAN-FD channels in high-end variants) for in-vehicle networking, with legacy CAN and LIN interfaces (up to 24 LIN channels) for lower-speed device communication. Many TC3xx devices also integrate up to two FlexRay controllers for time-triggered automotive networks (maintaining compatibility with earlier automotive communication standards). For high-bandwidth data, a Gigabit Ethernet MAC is included, enabling uses like automotive Ethernet (e.g., audio-video bridging and IP-based connectivity).
* '''Analog and Timers:''' A suite of analog peripherals including multiple ADC units for sensor interfacing and motor control, and DACs in some models. Sophisticated timer units are on-chip, notably the Generic Timer Module (GTM) and Capture/Compare Units (CCU6), which can generate complex PWM waveforms and handle events for engine control, power inverters, or robotics with minimal CPU intervention. These timers enable precise control of actuators (e.g. fuel injection timing, electric motor commutation) in real time.
*'''Serial Interfaces:''' SPI, I²C, UART/LIN and other serial interfaces for connecting to external sensors, actuator controllers, and memory. The controllers often support multiple instances (several SPI channels, etc.) to accommodate numerous devices. AURIX™ TC3xx also provides an external bus interface (EBU) for parallel memory or FPGA connectivity, and an SD/MMC interface (eMMC) to connect external flash memory for data logging or over-the-air update storage.
*'''Dedicated Processing Units:''' Some AURIX™ TC3xx models include special accelerators, such as a hardware Fast Fourier Transform unit (HW-FFT) and up to two Signal Processing Units (SPUs) optimized for radar signal processing. These enable the microcontroller to handle radar front-end data or other intensive DSP tasks (like Fourier transforms for radar or audio signals) on-chip, which is crucial for advanced driver assistance sensors. There is also a ''Security Module'' (covered in a later section) and a Safety Management Unit that supervise system integrity.
*'''Other On-chip Modules:''' Watchdog timers, error-correction coders for memories (ECC on flash and RAM for reliability), a programmable interrupt system, multiple DMA channels (up to 128 DMA channels) for efficient data movement, and debug interfaces (JTAG and a 2/3-pin DAP) for development. The on-chip debug system supports tracing of program execution (via a built-in Emulation Memory, MCDS) to aid in complex multicore software development.

Overall, the AURIX™TC3xx provides a highly integrated SoC-like platform, allowing a single chip to manage tasks ranging from powertrain control and chassis control to infotainment gateways. This high level of integration reduces the need for separate companion chips and helps to lower system complexity and cost.
===Performance and Benchmarking===
Fabricated in a 40 nm embedded flash process<ref name="ref2022357806" />, AURIX™ TC3xx processors achieve significant performance gains over prior generations while maintaining automotive-grade power efficiency. With six 32-bit cores at 300 MHz (four of them paired in lockstep), a flagship TC3xx device (e.g., TC39x) can deliver up to approximately 2,400 DMIPS of aggregate computing throughput<ref name="ref2022357806" />. In terms of per-core performance, the TriCore™ architecture yields around 1.3–2.0 DMIPS/MHz depending on the instruction mix, meaning each 300 MHz core can approach ~400–600 DMIPS in optimized scenarios<ref name="ref14281090103" /><ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. This is on par with or exceeding many contemporary 32-bit automotive MCUs. The integrated DSP extensions and optional accelerators (like the FFT unit) also enable high-speed signal processing, with Infineon citing up to ~1.8 GFLOPS of DSP throughput for certain operations<ref name="ref1222155140" />.

Real-world performance improvements of the TC3xx over its predecessor are notable: for example, compared to the first-generation AURIX™ (which offered up to 740 DMIPS), the TC3xx’s expanded core count and clock speed provide roughly three times the computational power on the same type of workload<ref name="ref14281090103" />. This extra headroom allows more functions (such as running multiple control algorithms or sensor fusion tasks in parallel) to be consolidated onto one microcontroller without compromising real-time deadlines<ref name="ref14281090103" />. Despite the increase in speed and core count, the TC3xx family was designed with power and thermal constraints in mind, achieving these gains within similar power consumption envelopes as the previous generation by leveraging the smaller 40 nm process and power-saving features like clock gating<ref name="ref5727814512" />. The deterministic real-time performance (with features like lockstep and tightly-coupled memory) makes the AURIX™ TC3xx suitable for the most demanding automotive applications, where consistent low latency and high throughput are required simultaneously.

== On-Chip System Connectivity and Bridges ==
[[File:TC3xx On-Chip System Connectivity.png|thumb|The TC3xx has two '''SRI Domains''' (SRI0 and SRI1). CPU0 to CPU3 are connected to SRI0, CPU4/5 are connected to SRI1.|alt=TC3xx On-Chip System Connectivity|423x423px]]
The AURIX™ TC3xx Platform has three independent on-chip connectivity resources:

* '''System Resource Interconnect Fabric (SRI Fabric)''' connects the TriCore™ CPUs, the DMA module, and other high bandwidth requestors to high bandwidth memories and other resources for instruction fetches and data accesses. A key component of the fabric is the SRI crossbar, which connects all the agents in one SRI domain. The SRI crossbar carries the transactions between the SRI Masters and SRI Slaves of the domain. The SRI crossbar supports parallel transactions between different SRI Master and SRI Slave agents. In addition to the parallelism of concurrent requests, it also supports pipelined requests from an SRI Master to a SRI Slave.
* '''System Peripheral Bus (SPB)''' connects the TriCore™ CPUs, the DMA module, and other SPB masters to the medium and low bandwidth peripherals. SPB masters do not directly connect to the SRI Fabric, and will access SRI attached resources via a SFI_F2S Bridge.
* '''Back Bone Bus (BBB)''' connects the TriCore™ CPUs, the DMA module, and SPB masters with ADAS resources. SRI Masters do not directly connect to the BBB, but access BBB attached resources via a SFI_S2F Bridge. SPB masters also do not directly connect to the BBB, but access BBB attached resources via bridging over the SRI Fabric.

=== CPU Resource Access Times ===
These tables describe the CPU access times to various resources in CPU clock cycles for the AURIX™ TC3xx Platform. In the case of load or fetch accesses, the access times are the minimum number of CPU stall cycles to complete the access. If there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

For write access, the access times are the maximum for a sequence of such access (non-conflicting). In many cases for a singleton access, or a short sequence, write buffering reduces the stall effect seen by a CPU, sometimes to 0. However, as with loads and fetches, if there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

==== Access latency for global resources ====
{| class="wikitable"
|+
! CPU Access Type !! CPU stall cycles
!Notes
|-
| Data read from System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
| rowspan="2" |The final number of stall cycles will depend on the real number of WS generated by the target resource.
|-
| Data write to System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC39x, TC37xED) || <math>9 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
| rowspan="2" |When SFI_S2F is connected to XBar2 (TC39x and TC37xED) there is an additional latency due to access going through an S2S.
|-
| Data write to Back Bone Bus (BBB) (TC39x, TC37xED) || <math>5 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC35x, TC33xED) || <math>6 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
|
|-
| Data write to Back Bone Bus (BBB) (TC35x, TC33xED) || <math>3 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|
|}


* '''Module Wait State''': The number of wait states for read and for write accesses is >= 1 and depends on the accessed module and its configuration.


==== CPU Accesses: Stall cycles for local and SRI resources ====
{| class="wikitable"
|+
! CPU Access Type !! Local CPU !! Local SRI !! Remote SRI Domain
|-
| Data read from DSPR || 0 || 7 || 10
|-
| Data write to DSPR || 0 || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from DSPR || See local SRI column || 7 || 10
|-
| Data read from DLMU || 0 || 7 || 10
|-
| Data write to DLMU || 2 || 5, {{rev|3|with Pipelining}}|| 5, 4
|-
| Instruction fetch from DLMU || See local SRI column || 7 || 10
|-
| Data read from PSPR || See local SRI column || 7 || 10
|-
| Data write to PSPR || See local SRI column || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from PSPR || 0 || 7 || 10
|-
| Data read from PFlash || 5 + PWS || 10 + PWS || 13 + PWS
|-
| Instruction fetch from PFlash (buffer miss) || 2 + PWS || 9 + PWS || 12 + PWS
|-
| Instruction fetch from PFlash (buffer hit) || 3 || 6 || 9
|-
| Data read from LMU || n.a. || 7 || 10
|-
| Data write to LMU || n.a. || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from LMU || n.a. || 7 || 10
|-
| Data read from DFlash || n.a. || 5 + 3*(3 + DCWS) || 8 + 3*(3 + DCWS)
|-
| Data read access from EMEM (TC39x, TC37xED) || n.a. || n.a. || 14, {{rev|15|fBBB < fSRI}}
|-
| Data write access to EMEM (TC39x, TC37xED) || n.a. || n.a. || 9
|-
| Data read access from EMEM (TC35x, TC33xED) || n.a. || 11, {{rev|12|fBBB < fSRI}}|| n.a.
|-
| Data write access to EMEM (TC35x, TC33xED) || n.a. || 9 || n.a.
|-
| Data read access from DAM || n.a. || 10 || 13
|-
| Data write access to DAM || n.a. || 7 || 7
|}

* '''Remote SRI Domain''': Only applies to products with SRI extenders. Additional latency due to access going through an S2S
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''DCWS''': Configured DFlash Corrected Wait States (Includes cycles for DFlash access cycles and ECC correction latency)

== CPU Subsystem ==
[[File:TC3xx Processor Core, Local Memory and Connectivity.png|alt=TC3xx Processor Core, Local Memory and Connectivity|thumb|Processor Core, Local Memory and Connectivity]]The Infineon AURIX™ TC3xx features up to 6 processor cores (CPU0 ... CPU5) implementing the [[TriCore Instruction Set Architecture|TC1.6.2 instruction set architecture]]. The following section focuses on the microarchitectural details of the CPU subsystem. For more information about the ISA, please take a look at the [[TriCore Instruction Set Architecture]].

The processor core connects to the following memories and bus interfaces (where implemented):
*Program Scratch-Pad SRAM (PSPR)
*Data Scratch-Pad SRAM (DSPR)
*Program Cache (PCache)
*Data Cache (DCache)
*Local Memory Unit (DLMU)
*Local Pflash bank (LPB)
*SRI slave interface (x2)
*SRI master Interface
*SPB master interface

=== TC1.6.2P Implementation Features ===
*Most instructions executed in 1 cycle
*Branch instructions in 1, 2 or 3 cycles (using dynamic branch prediction)
*Wide memory interface for fast context switch
* Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
*Six memory protection register sets
*Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
*Third pipeline for loop instruction only (zero overhead loop)
*Single precision Floating Point Unit (IEEE-754 Compatible)
*Dedicated Integer divide unit
*18 data memory protection ranges, 10 code memory protection ranges arranged in 6 sets

=== Superscalar Architecture ===
The processor core within the AURIX™ TC3xx family, specifically the TC1.6.2P implementation, employs a superscalar architecture characterized by three parallel pipelines: the Integer Pipeline, the Load/Store Pipeline, and the Loop Pipeline. Superscalar execution is a form of instruction-level parallelism that enables the processor to issue and execute multiple instructions during a single clock cycle. The TriCore™ TC3xx core's superscalar architecture allows it to issue and execute multiple instructions in parallel. Specifically, it can issue up to two instructions simultaneously to the Integer and Load/Store pipelines. However, there are certain constraints on this dual issuing capability. For example, back-to-back data arithmetic instructions can only be issued in separate cycles, and a load/store instruction can be issued either on its own or paired with a data arithmetic instruction, provided the load/store instruction is the second in the pair. Under ideal conditions, with careful instruction scheduling, this dual-issue capability can lead to a throughput of close to 0.5 clock cycles per instruction, effectively executing two instructions per cycle.

=== Pipeline Stages ===
The execution of instructions within the TriCore™ TC3xx core is managed through a pipeline consisting of several stages. In one document it is mentioned that the pipeline consists of 6 stages <ref name="ref3635926" />, but the exact stages remain unclear. From the architecture the following stages can be inferred:

* '''Fetch Stage''': The initial stage in the pipeline is the Fetch stage, where instructions are retrieved from memory. This task is handled by the Instruction Fetch Unit (IFU), which is responsible for fetching instructions from the memory system. To improve efficiency, the IFU employs a pre-fetching mechanism, anticipating the instructions that will be needed and bringing them into the processor before they are actually required. Instructions are fetched through a 64-bit wide Program Memory Interface (PMI), allowing for the retrieval of a significant amount of instruction data in each cycle. The fetched instructions are then placed into an issue FIFO, a buffer capable of holding up to six instructions. This buffer plays a crucial role in managing the flow of instructions to the subsequent execution pipelines. The 64-bit fetch width and the instruction buffer are indicative of a design that aims to ensure a continuous supply of instructions to the pipelines, preventing them from being starved of work. A wider fetch path allows for more instruction bits to be obtained from memory in each clock cycle, while the buffer helps to mitigate temporary delays in instruction fetching.
* '''Execution Unit''': The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop Pipeline. All three pipelines operate in parallel and are capable of executing instructions simultaneously. Each pipline has its own decode stage and two execute stages. Furthermore, the TC3xx features a Floating Point Unit (FPU). It is not clear whether the FPU is part of the execution unit or a separate unit. It is assumed that the FPU also has its own decode stage and an unknown number of execute stages
** '''Decode Stage''': Following the Fetch stage, the instruction are issued to one of the pipelines. In the decode stage of each pipeline, the instruction is examined and translated to determine the specific operation it represents and to identify the operands it will operate on. It is assumed that operands are read from the register file during the decode stage.
** '''Execute Stage''': The Execute stage is where the actual operation specified by the instruction is carried out. Pipeline hazards (stalls) are minimised by the use of forwarding paths between pipeline stages allowing the results of one instruction to be used by a following instruction as soon as the result becomes available.
** '''Writeback Stage''': The final stage in the pipeline is the Writeback stage. In this stage, the results produced by the executed instruction are written back to the processor's register file, making them available for subsequent instructions. It is unclear whether the writeback stage is part of the (two) execution stages or a separate stage.

=== Execution Pipelines ===
The TriCore™ TC3xx core leverages four parallel pipelines to enhance its performance. Each pipeline is designed to handle a specific class of instructions:

* '''Integer Pipeline:''' This pipeline is responsible for executing integer arithmetic and logical instructions, including data-conditional jump instructions, bit manipulation operations, as well as division and multiply-accumulate (MAC) instructions.
* '''Load/Store Pipeline:''' The primary function of this pipeline is to manage memory access operations, including loading data from memory and storing data to memory. It also handles address arithmetic, unconditional jump instructions, procedure call instructions, context-switching operations, and control flow related to context save areas (CSAs).
* '''Loop Pipeline:''' This is a specialized pipeline designed to facilitate zero-overhead loops, a technique that significantly improves the performance of iterative code sections. Its design aims to eliminate or minimize the overhead typically associated with loop control, such as incrementing counters and checking loop conditions. Some documentation suggests that the loop pipeline comes along with a "Loop Cache". This dedicated cache would likely be used to store instructions belonging to the loop, enabling very fast access and execution for repeated iterations.
* '''Floating Point Unit (FPU):''' The FPU is responsible for executing floating-point arithmetic operations

=== Store Buffers ===
The TriCore™ TC3xx core include '''Store Buffers''' to decouple memory write operations from CPU instruction execution. All stores from the Load/Store Pipeline are placed in the store buffer prior to being written to local memory or transferred via the bus system. Write data is taken from the store buffers and written to memory when the target memory or bus interface becomes available. In normal operation the CPU will prioritise memory load operations over store operations in order to improve performance unless the store buffer is full or the order of load and store operations must be preserved (e.g. peripheral space access). The store buffer can hold the data for up to 6 stores operations. To improve performance the store buffer will merge consecutive byte, half-word, and word writes of the same location to reduce the number of memory accesses required.

=== Instruction Timing ===

==Functional Safety and Security Features==
===Hardware Security Module and Encryption===
One of the defining features of the AURIX™ TC3xx family is its robust hardware-based security subsystem, implemented to protect against cyber threats and unauthorized manipulation of vehicle systems. Each TC3xx MCU includes a dedicated ''Hardware Security Module'' (HSM), which is essentially an on-chip co-processor with its own CPU and cryptographic engine designed to handle secure operations. In the second-generation AURIX™ (TC3xx), the HSM was upgraded with support for asymmetric cryptography (e.g., RSA, ECC algorithms) in hardware, providing significantly faster public-key encryption and authentication capabilities than pure software implementations. This HSM supports '''EVITA Full''' (the highest level of the EU’s EVITA automotive security requirements), meaning it can perform secure boot, message authentication, and encryption at a level suitable for protecting critical in-vehicle communications. For example, the HSM can encrypt and authenticate CAN/Ethernet messages to prevent spoofing or tampering on the vehicle network, and it can manage cryptographic keys securely isolated from the main application cores.<ref name="ref14281090104">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref2022357806" />

The security module enables features like '''secure boot''', where the AURIX™ will only execute firmware that is digitally signed by the vehicle manufacturer, thereby preventing unauthorized or malicious code. It also facilitates ''over-the-air (OTA) updates'' in a secure manner: the TC3xx HSM can verify and decrypt update packages received via telematics, allowing firmware upgrades while protecting against attackers attempting to hijack the software. In addition, the HSM includes a true random number generator and supports protocols for immobilizer and theft protection systems. Infineon’s implementation essentially treats the HSM as an “embedded smart card” inside the microcontroller. This approach, building on Infineon’s expertise in chip card security, helps to safeguard sensitive assets like cryptographic keys and to perform secure operations (encryption, decryption, authentication) in hardware, making attacks significantly more difficult. The strong cybersecurity provisions of the AURIX™ TC3xx have made it a preferred choice for vehicle gateway ECUs and central body controllers, which are points of entry for connected car communications and thus high-value targets for hackers. By incorporating the HSM, automotive OEMs can implement advanced security features such as encrypted onboard communication (to thwart bus tampering) and secure diagnostics, ensuring the vehicle’s electronic data is protected against cyber threats even as cars become more connected.<ref name="ref14281090104" /><ref name="ref5727814513">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref><ref name="ref19484776953">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
=== Functional Safety and Fault Tolerance===
Beyond cybersecurity, the AURIX™ TC3xx architecture is built with extensive ''functional safety'' features to meet the highest safety integrity levels in automotive systems. The multi-core design supports ''lockstep operation'', where redundant checker cores run in parallel with main cores and continuously compare results cycle-by-cycle. In TC3xx devices, up to four of the six TriCore™ CPUs have such lockstep partner cores, allowing the microcontroller to detect any single-point CPU failure instantly (if a discrepancy arises between the core and its checker, a fault is signaled). A ''Safety Management Unit (SMU)'' is integrated on-chip to monitor various fault conditions throughout the device – it aggregates error signals from the lockstep cores, memory ECC monitors, clock/watchdog monitors, and peripheral self-tests, and can initiate safe-state actions (like resetting the chip or signaling an error pin to an external supervisor) if a critical fault is detected. The AURIX™ safety concept also includes a distributed Memory Protection Unit (MPU) arrangement, with multiple memory protection contexts that prevent errant or malicious code from writing to wrong memory areas. This helps contain faults and eases the integration of software with mixed criticality (Infineon allows partitioning software components of different ASIL levels on the same MCU while keeping them isolated).<ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref19519075552">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref>

Crucially, the TC3xx family was developed according to ISO 26262 processes and can achieve '''ASIL-D''' (Automotive Safety Integrity Level D), the highest grade for automotive functional safety. Compared to a traditional dual-core lockstep approach, the AURIX’s™ multi-core safety architecture allowed Infineon to reduce certain safety development overheads (earlier Infineon data suggested up to 30% reduction in safety software workload) by providing built-in safety mechanisms and diagnostics. Infineon supplies a comprehensive safety manual and diagnostic libraries for the AURIX™, helping engineers utilize features like CPU self-tests, RAM tests, and CRC checks to comply with safety standards. In addition to automotive standards, the AURIX™ TC3xx has also been qualified for '''industrial safety''': in 2023, Infineon announced support for IEC 61508 metrics, enabling designs with AURIX™ to reach SIL-2 and SIL-3 safety integrity levels for industrial applications. This cross-industry safety compliance is facilitated by the MCU’s redundant design and detailed failure mode documentation (FMEDA) provided by Infineon. In summary, the AURIX™ TC3xx integrates both proactive safety (fault prevention via lockstep, monitoring and protection) and reactive safety (fault detection and safe shutdown), making it a dependable component for systems that cannot afford unintended behavior, whether in cars, factories, or aerospace. <ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref4967712052">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref><ref name="ref196858272">MCUs support industrial functional safety - Electronic Products https://www.electronicproducts.com/mcus-support-industrial-functional-safety/</ref>
== Platform Devices ==
The following table shows a feature overview of the AURIX™ TC3xx Platform family focusing on memory and number of cores.
{| class="wikitable"
!
!Feature
!TC33x
!TC33xEXT
!TC35x
!TC36x
!TC37x
!TC37xEXT
!TC38x
!TC39x
|-
| rowspan="2" |CPUs
|Cores / Checker Cores
|1 / 1
|2 / 1
|3 / 2
|2 / 2
|3 / 2
|3 / 3
|4 / 2
|6 / 4
|-
|Max. Freq.
| colspan="8" |300 MHz
|-
| rowspan="2" |Cache per CPU
|Program [KB]
| colspan="8" |32
|-
|Data [KB]
| colspan="8" |16
|-
| rowspan="3" |SRAM per CPU
|PSPR [KB]
|8
|{{rev|32|CPU0}}
{{rev|64|other}}
|64
|32
|64
|64
|64
|64
|-
|DSPR [KB]
|192
|{{rev|192|CPU0}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|192
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|-
|DLMU [KB]
|8
|{{rev|8|CPU0}}
{{rev|64|other}}
|64
|64
|64
|64
|64
|64
|-
| rowspan="2" |SRAM global
|LMU [KB]
| -
| -
|512
| -
| -
| -
|128
|768
|-
|DAM [KB]
| -
| -
|32
| -
|64
|64
|128
|128
|-
| rowspan="3" |Extension Memory (EMEM)
|TCM [MB]
| -
|1
|2
| -
| -
|2
| -
|2
|-
|XCM [MB]
| -
| -
| -
| -
| -
|1
| -
|2
|-
|XTM [KB]
| -
|16
|16
| -
| -
|16
| -
|16
|-
| rowspan="2" |Program Flash
|Size [MB]
|2
|4
|4
|4
|6
|10
|10
|16
|-
|Banks [MB]
|1 x 2
|2 x 2
|2 x 2
|2 x 2
|2 x 3
|3 x 3, 1 x 1
|3 x 3, 1 x 1
|5 x 3, 1 x 1
|-
| rowspan="2" |Data Flash
|DF0 Size (single-ended) [KB]
|128
|128
|128
|128
|256
|512
|512
|1024
|-
|DF1 Size (single-ended) [KB]
|128
|128
|128
|128
|128
|128
|128
|128
|-
| rowspan="3" |DMA
|Channels
|64
|64
|64
|64
|128
|128
|128
|128
|-
|Move Engines
|2
|2
|2
|2
|2
|2
|2
|2
|-
|Resource Partitions
|4
|4
|4
|4
|4
|4
|4
|4
|}

== Compilers ==
The AURIX™ TC3xx family is a series of high-performance microcontrollers widely used in automotive and industrial applications. Compilers for the AURIX™ TC3xx are crucial for developers aiming to optimize performance, reliability, and safety in their applications. One significant aspect of the compiler landscape for AURIX™ TC3xx is the limited direct support from mainline open-source compilers such as GCC or LLVM/Clang. The primary reason for this is the stringent requirements for functional safety in automotive and industrial applications, which demand specialized features and compliance with safety standards that are often not met by general-purpose open-source compilers.

=== Commercial Compilers ===

# '''Tasking''': Tasking compilers are renowned for their robust support for automotive applications, offering advanced debugging capabilities and optimization techniques tailored for the AURIX™ architecture. They provide extensive code optimization, comprehensive debugging tools, and strong support for safety standards such as ISO 26262, making them ideal for developing high-performance, reliable, and safe applications.
# '''HighTec''': The HighTec compiler is a popular choice, known for its Eclipse-based development environment and strong multicore support. HighTec provides both GCC and LLVM-based ports of open-source compilers tailored specifically for the AURIX™ TC3xx family. These compilers offer efficient parallel execution, advanced code analysis, and an integrated development environment, ensuring robust performance and compliance with safety standards.
# '''Green Hills Software''': Green Hills Software provides a highly optimized toolchain aimed at safety-critical applications, focusing on high performance and strict compliance with automotive standards. Their compiler offers superior optimization, extensive safety features, and a proprietary IDE with specialized tools for automotive development, ensuring developers can meet the stringent demands of functional safety.

=== GCC for AURIX™ ===

While mainline GCC does not directly support the AURIX™ TC3xx family, there is an unofficial GCC version available for AURIX™. Due to the GNU General Public License (GPL), the source code from HighTec was retrieved and, along with binary versions, published on GitHub:

*GCC 4.9.4/Binutils 2.20/Newlib 1.18 for Tricore™ AURIX™ [[https://github.com/volumit/package_494 Source]] [[https://github.com/volumit/tricore_gcc494_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc494_linux_bins Prebuild Linux Binaries]]
*GCC 9.4.0/Binutils 2.20/Newlib 1.18 for Tricore™ AURIX™ [[https://github.com/volumit/package_940 Source]] [[https://github.com/volumit/tricore_gcc940_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc940_linux_bins Prebuild Linux Binaries]]
*GDB 10.0.50 for Tricore™ AURIX™ [[https://github.com/volumit/gdb-tricore Source]]
==emmtrix Tools for AURIX™ TC3xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX™ TC3xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===
====Architecture & Variant Consulting====
* Support in selecting suitable AURIX derivatives for new product generations (trade-offs between performance, price, safety, and peripheral features)
*Analysis of requirements and mapping to specific AURIX product families (e.g., TC3xx vs. TC4xx)
*Analysis/identification of performance margins for down- or upgrades
==== Runtime Analysis & Performance Engineering ====
* Execution of detailed runtime analyses (maximum/minimum vs. average)
* Identification of bottlenecks in program execution, including benchmarking
*Optimization of access to flash, RAM, and peripherals (e.g., cache configuration, DMA utilization)
====Dependency Analysis====
*Freedom from interference (ASIL level check)

==== Multicore Design & Scheduling Concepts ====

* Development of core mapping strategies (static vs. dynamic assignment of compute-intensive tasks)

*Support for integrating bare-metal scheduling on AURIX
*Assistance with architectural decisions to meet functional safety requirements in multicore systems

==== Training & Know-how Transfer ====

* Technical in-house workshops on AURIX optimization, multicore strategies

*Coaching of employees/project teams in performance analysis and systematic tuning
==See Also==

*[[Infineon AURIX TC4x|Infineon AURIX™ TC4x]]
*[[Infineon AURIX TC2xx|Infineon AURIX™ TC2xx]]
*[[TriCore Instruction Set Architecture]]

==External Links==

*https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/
*[https://documentation.infineon.com/aurixtc3xx/docs/qmd1702366622648 AURIX™ TC3xx user manuals]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d3605221d96 AURIX™ TC3xx User Manual Part-1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d35f8541d94 AURIX™ TC3xx User Manual Part-2]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd AURIX™ TC3xx Architecture vol 1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 AURIX™ TC3xx Architecture vol 2]

== References ==
<references />
[[Category:Supported Architectures]]

{{#seo:
|title=Infineon AURIX TC3xx Family – Deep Dive
|description=This deep dive into Infineon's AURIX TC3xx family explores its multi-core TriCore architecture, real-time capabilities, safety and security features and tools
|image=File:AURIX_TC399_LFBGA-516_plain.jpg
|keywords=AURIX, Infineon, TC3xx, microcontroller, TriCore, automotive, ADAS, ISO 26262, functional safety, embedded security, ASIL-D, deep dive
}}

Infineon AURIX TC3xx

2025-05-21T08:15:37Z

Mira.steinmetz:

[[File:AURIX TC399 LFBGA-516 plain.jpg|thumb|Infineon AURIX™ TC3xx second-generation microcontroller (TC399 BGA package). The AURIX™ TC3xx family integrates multiple TriCore™ CPUs and on-chip safety/security modules for automotive applications.|alt=TC399 BGA package]]
The '''Infineon AURIX™ TC3xx''' (Automotive Realtime Integrated neXt-generation architecture) is a family of 32-bit automotive microcontrollers introduced as the second generation of Infineon’s AURIX™ platform. Launched in 2016 as a successor to the earlier [[Infineon AURIX TC2xx|AURIX™ TC2xx series]], the TC3xx devices emphasize high performance, functional safety, and embedded security for advanced automotive and industrial applications. AURIX™ TC3xx microcontrollers feature a hexa-core [[TriCore Instruction Set Architecture|''TriCore'' processor architecture]] with enhanced safety measures, making them well-suited for demanding tasks such as autonomous driving domain controllers, powertrain control, and sensor data fusion in advanced driver-assistance systems (ADAS). The combination of multiple CPU cores, extensive on-chip memory, and a rich peripheral set allows TC3xx chips to deliver real-time responsiveness and reliability in safety-critical environments while meeting stringent automotive standards (such as ISO 26262 for functional safety).<ref name="ref1951907555">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref><ref name="ref1428109010">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref1948477695">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
==Applications==
AURIX™ TC3xx microcontrollers are used in a variety of safety-critical and high-performance applications across the automotive and industrial sectors. Key application domains include:
*'''Automotive Systems:''' The TC3xx family was primarily designed for automotive use and finds broad application in vehicles’ electronic control units (ECUs). Notably, it is used in ''powertrain and drivetrain control'' (engine management, transmission control, hybrid/electric vehicle inverter control, battery management) where its real-time processing and resilience support precise actuator control. It is also deployed in ''chassis and safety systems'' such as anti-lock braking systems (ABS), electronic stability control, airbag controllers, and electric power steering, leveraging its redundancy and fast response for fail-safe operation. With the growth of ADAS and autonomous driving, AURIX™ TC3xx devices serve as domain controllers for ''ADAS sensor fusion'', handling data from radar, LiDAR, camera, and ultrasonic sensors and performing environment modeling and decision-making algorithms. Their combination of multiple cores and a built-in radar signal processing sub-system makes them an attractive choice for tasks like front radar processing, sensor fusion hubs, and ''autonomous driving domain controllers'' that must meet ASIL-D safety levels.<ref name="ref14281090102">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
*'''Industrial Automation and Robotics:''' Infineon has also positioned the AURIX™ family for use in industrial applications that demand high reliability. The TC3xx MCUs, with their hardware self-test mechanisms and safety documentation, can be found in ''industrial motor drives, robotics controllers, and PLCs (programmable logic controllers)'', where they help achieve functional safety certifications up to SIL-3 (according to IEC 61508). The powerful TriCore™ cores and rich peripheral set enable complex motor control algorithms (e.g., field-oriented control for servo motors) and real-time sensor processing in factory automation. Additionally, the support for automotive-grade networking (CAN/CAN-FD, Ethernet) and timing peripherals makes them suitable for synchronous control in robotics and machinery. Infineon’s provision of AUTOSAR-compatible software for AURIX™ has even facilitated its use in non-automotive settings such as medical devices and elevator controllers, where proven safety and security are required.<ref name="ref496771205">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref>
*'''Aerospace and Defense:''' The high fault-tolerance and deterministic performance of the AURIX™ TC3xx architecture also attract interest for aerospace and other mission-critical uses. In avionics systems or autonomous drones, for instance, the lockstep core configuration and robust error checking of AURIX™ can provide an added layer of reliability for flight control computers or navigation systems. While primarily an automotive chip, its ability to operate in harsh conditions (−40°C to 150°C range) and to detect internal failures in real-time makes it viable for certain aerospace electronic systems. Some defense and aerospace projects leverage COTS (commercial off-the-shelf) automotive components like AURIX™ for applications such as unmanned vehicle control and high-reliability communication links, given its safety pedigree. (In these domains, additional analysis and possibly radiation testing would be performed if the devices are used in high-altitude or space environments.)
== Architecture Overview ==
[[File:Infineon TC3xx Architecture.webp|545x545px|thumb|alt=TC3xx Architecture Overview|TC3xx Architecture Overview]]
=== Processor Cores and Architecture===
The AURIX™ TC3xx family implements Infineon’s TriCore™ architecture, which uniquely combines aspects of RISC microcontrollers, DSP (digital signal processor) capabilities, and conventional microprocessor features into a single core design. Each TC3xx device can include up to six independent TriCore™ 32-bit CPU cores (TriCore™ version 1.6.2), all capable of running at up to 300 MHz clock frequency. Four of these cores can operate in dual-core lockstep pairs (with one core acting as a redundant checker for its partner) to provide fault detection for safety-critical functions. The TriCore™ cores use a superscalar Harvard architecture with 32-bit instruction words (and support for mixed 16/32-bit instruction encoding for code density). Each core includes a dedicated Floating Point Unit (FPU) for single-precision arithmetic and supports DSP-oriented instructions (e.g. single-cycle 16×16 MAC operations, SIMD for 16-bit/8-bit data) to accelerate signal processing tasks. For fast real-time performance, the architecture offers low interrupt latency (with automatic context save on-chip) and features like zero-overhead loops and a programmable peripheral timer unit for scheduling tasks. In total, a high-end TC3xx (such as the TC39x) provides six 300 MHz cores plus four checker cores, yielding a theoretical processing throughput of up to ~2400 DMIPS (Dhrystone MIPS) when all cores are utilized. This represents roughly a threefold increase in computational power over the previous AURIX™ generation (which achieved ~740 DMIPS with three cores).<ref name="ref19484776952">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref><ref name="ref2022357806">UDE Debug, Trace and Test solutions for Infineon TriCore™ AURIX™ TC32, TC33, TC35, TC36, TC37, TC38, TC39, TC3x Microcontrollers https://www.pls-mc.com/products/infineon-tricore-aurix-tc32-tc33-tc35-tc36-tc37-tc38-tc39-microcontrollers/</ref><ref name="ref14281090103">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref>
===Memory Subsystem and Cache===
AURIX™ TC3xx microcontrollers integrate a large on-chip memory system to meet real-time and safety requirements. Program flash memory sizes range up to 16 MB on the largest models, with over 6 MB of on-chip SRAM available for data and scratchpad usage. Each TriCore™ CPU has its own tightly-coupled local memories as well as caches: for example, each core includes a 32 KB instruction cache and a 16 KB data cache. In addition, every core has separate local RAM blocks (Harvard architecture) for instructions and data (often termed PSPR and DSPR – Program Scratch-Pad RAM and Data Scratch-Pad RAM) that allow deterministic access for time-critical routines. Shared global memory is provided via a Local Memory Unit (LMU) which can be up to several hundred kilobytes (for instance, 768 KB in the TC39x) accessible by all cores. The memory system is connected by a high-bandwidth internal bus fabric (the SRI crossbar and peripheral buses) that arbitrates access between cores, DMA engines, and peripherals. This architecture ensures that each core can quickly fetch instructions and data either from its local cache/RAM or the central memory, enabling efficient parallel processing. Memory protection hardware is also built-in to isolate tasks of different criticality, an important feature for safety and security.<ref name="ref19484776952" /><ref name="ref5727814512">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
===Peripherals and Interfaces===
One of the strengths of the AURIX™ TC3xx architecture is its extensive set of on-chip peripherals and interface controllers, designed to handle the complex networking and I/O needs of modern vehicles and industrial systems. Key peripheral features and interfaces include:<ref name="ref19484776952" /><ref name="ref2022357806" /><ref name="ref14281090103" /><ref name="ref3635926">AURIX™ Training System Architecture https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_System_Architecture-Training-v01_00-EN.pdf?fileId=5546d46272e49d2a0172eb476d56739e</ref>

* '''Networking Interfaces:''' Multiple CAN FD controllers (supporting up to 12 CAN-FD channels in high-end variants) for in-vehicle networking, with legacy CAN and LIN interfaces (up to 24 LIN channels) for lower-speed device communication. Many TC3xx devices also integrate up to two FlexRay controllers for time-triggered automotive networks (maintaining compatibility with earlier automotive communication standards). For high-bandwidth data, a Gigabit Ethernet MAC is included, enabling uses like automotive Ethernet (e.g., audio-video bridging and IP-based connectivity).
* '''Analog and Timers:''' A suite of analog peripherals including multiple ADC units for sensor interfacing and motor control, and DACs in some models. Sophisticated timer units are on-chip, notably the Generic Timer Module (GTM) and Capture/Compare Units (CCU6), which can generate complex PWM waveforms and handle events for engine control, power inverters, or robotics with minimal CPU intervention. These timers enable precise control of actuators (e.g. fuel injection timing, electric motor commutation) in real time.
*'''Serial Interfaces:''' SPI, I²C, UART/LIN and other serial interfaces for connecting to external sensors, actuator controllers, and memory. The controllers often support multiple instances (several SPI channels, etc.) to accommodate numerous devices. AURIX™ TC3xx also provides an external bus interface (EBU) for parallel memory or FPGA connectivity, and an SD/MMC interface (eMMC) to connect external flash memory for data logging or over-the-air update storage.
*'''Dedicated Processing Units:''' Some AURIX™ TC3xx models include special accelerators, such as a hardware Fast Fourier Transform unit (HW-FFT) and up to two Signal Processing Units (SPUs) optimized for radar signal processing. These enable the microcontroller to handle radar front-end data or other intensive DSP tasks (like Fourier transforms for radar or audio signals) on-chip, which is crucial for advanced driver assistance sensors. There is also a ''Security Module'' (covered in a later section) and a Safety Management Unit that supervise system integrity.
*'''Other On-chip Modules:''' Watchdog timers, error-correction coders for memories (ECC on flash and RAM for reliability), a programmable interrupt system, multiple DMA channels (up to 128 DMA channels) for efficient data movement, and debug interfaces (JTAG and a 2/3-pin DAP) for development. The on-chip debug system supports tracing of program execution (via a built-in Emulation Memory, MCDS) to aid in complex multicore software development.

Overall, the AURIX™TC3xx provides a highly integrated SoC-like platform, allowing a single chip to manage tasks ranging from powertrain control and chassis control to infotainment gateways. This high level of integration reduces the need for separate companion chips and helps to lower system complexity and cost.
===Performance and Benchmarking===
Fabricated in a 40 nm embedded flash process<ref name="ref2022357806" />, AURIX™ TC3xx processors achieve significant performance gains over prior generations while maintaining automotive-grade power efficiency. With six 32-bit cores at 300 MHz (four of them paired in lockstep), a flagship TC3xx device (e.g., TC39x) can deliver up to approximately 2,400 DMIPS of aggregate computing throughput<ref name="ref2022357806" />. In terms of per-core performance, the TriCore™ architecture yields around 1.3–2.0 DMIPS/MHz depending on the instruction mix, meaning each 300 MHz core can approach ~400–600 DMIPS in optimized scenarios<ref name="ref14281090103" /><ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. This is on par with or exceeding many contemporary 32-bit automotive MCUs. The integrated DSP extensions and optional accelerators (like the FFT unit) also enable high-speed signal processing, with Infineon citing up to ~1.8 GFLOPS of DSP throughput for certain operations<ref name="ref1222155140" />.

Real-world performance improvements of the TC3xx over its predecessor are notable: for example, compared to the first-generation AURIX™ (which offered up to 740 DMIPS), the TC3xx’s expanded core count and clock speed provide roughly three times the computational power on the same type of workload<ref name="ref14281090103" />. This extra headroom allows more functions (such as running multiple control algorithms or sensor fusion tasks in parallel) to be consolidated onto one microcontroller without compromising real-time deadlines<ref name="ref14281090103" />. Despite the increase in speed and core count, the TC3xx family was designed with power and thermal constraints in mind, achieving these gains within similar power consumption envelopes as the previous generation by leveraging the smaller 40 nm process and power-saving features like clock gating<ref name="ref5727814512" />. The deterministic real-time performance (with features like lockstep and tightly-coupled memory) makes the AURIX™ TC3xx suitable for the most demanding automotive applications, where consistent low latency and high throughput are required simultaneously.

== On-Chip System Connectivity and Bridges ==
[[File:TC3xx On-Chip System Connectivity.png|thumb|The TC3xx has two '''SRI Domains''' (SRI0 and SRI1). CPU0 to CPU3 are connected to SRI0, CPU4/5 are connected to SRI1.|alt=TC3xx On-Chip System Connectivity|423x423px]]
The AURIX™ TC3xx Platform has three independent on-chip connectivity resources:

* '''System Resource Interconnect Fabric (SRI Fabric)''' connects the TriCore™ CPUs, the DMA module, and other high bandwidth requestors to high bandwidth memories and other resources for instruction fetches and data accesses. A key component of the fabric is the SRI crossbar, which connects all the agents in one SRI domain. The SRI crossbar carries the transactions between the SRI Masters and SRI Slaves of the domain. The SRI crossbar supports parallel transactions between different SRI Master and SRI Slave agents. In addition to the parallelism of concurrent requests, it also supports pipelined requests from an SRI Master to a SRI Slave.
* '''System Peripheral Bus (SPB)''' connects the TriCore™ CPUs, the DMA module, and other SPB masters to the medium and low bandwidth peripherals. SPB masters do not directly connect to the SRI Fabric, and will access SRI attached resources via a SFI_F2S Bridge.
* '''Back Bone Bus (BBB)''' connects the TriCore™ CPUs, the DMA module, and SPB masters with ADAS resources. SRI Masters do not directly connect to the BBB, but access BBB attached resources via a SFI_S2F Bridge. SPB masters also do not directly connect to the BBB, but access BBB attached resources via bridging over the SRI Fabric.

=== CPU Resource Access Times ===
These tables describe the CPU access times to various resources in CPU clock cycles for the AURIX™ TC3xx Platform. In the case of load or fetch accesses, the access times are the minimum number of CPU stall cycles to complete the access. If there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

For write access, the access times are the maximum for a sequence of such access (non-conflicting). In many cases for a singleton access, or a short sequence, write buffering reduces the stall effect seen by a CPU, sometimes to 0. However, as with loads and fetches, if there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

==== Access latency for global resources ====
{| class="wikitable"
|+
! CPU Access Type !! CPU stall cycles
!Notes
|-
| Data read from System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
| rowspan="2" |The final number of stall cycles will depend on the real number of WS generated by the target resource.
|-
| Data write to System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC39x, TC37xED) || <math>9 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
| rowspan="2" |When SFI_S2F is connected to XBar2 (TC39x and TC37xED) there is an additional latency due to access going through an S2S.
|-
| Data write to Back Bone Bus (BBB) (TC39x, TC37xED) || <math>5 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC35x, TC33xED) || <math>6 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
|
|-
| Data write to Back Bone Bus (BBB) (TC35x, TC33xED) || <math>3 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|
|}


* '''Module Wait State''': The number of wait states for read and for write accesses is >= 1 and depends on the accessed module and its configuration.


==== CPU Accesses: Stall cycles for local and SRI resources ====
{| class="wikitable"
|+
! CPU Access Type !! Local CPU !! Local SRI !! Remote SRI Domain
|-
| Data read from DSPR || 0 || 7 || 10
|-
| Data write to DSPR || 0 || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from DSPR || See local SRI column || 7 || 10
|-
| Data read from DLMU || 0 || 7 || 10
|-
| Data write to DLMU || 2 || 5, {{rev|3|with Pipelining}}|| 5, 4
|-
| Instruction fetch from DLMU || See local SRI column || 7 || 10
|-
| Data read from PSPR || See local SRI column || 7 || 10
|-
| Data write to PSPR || See local SRI column || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from PSPR || 0 || 7 || 10
|-
| Data read from PFlash || 5 + PWS || 10 + PWS || 13 + PWS
|-
| Instruction fetch from PFlash (buffer miss) || 2 + PWS || 9 + PWS || 12 + PWS
|-
| Instruction fetch from PFlash (buffer hit) || 3 || 6 || 9
|-
| Data read from LMU || n.a. || 7 || 10
|-
| Data write to LMU || n.a. || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from LMU || n.a. || 7 || 10
|-
| Data read from DFlash || n.a. || 5 + 3*(3 + DCWS) || 8 + 3*(3 + DCWS)
|-
| Data read access from EMEM (TC39x, TC37xED) || n.a. || n.a. || 14, {{rev|15|fBBB < fSRI}}
|-
| Data write access to EMEM (TC39x, TC37xED) || n.a. || n.a. || 9
|-
| Data read access from EMEM (TC35x, TC33xED) || n.a. || 11, {{rev|12|fBBB < fSRI}}|| n.a.
|-
| Data write access to EMEM (TC35x, TC33xED) || n.a. || 9 || n.a.
|-
| Data read access from DAM || n.a. || 10 || 13
|-
| Data write access to DAM || n.a. || 7 || 7
|}

* '''Remote SRI Domain''': Only applies to products with SRI extenders. Additional latency due to access going through an S2S
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''DCWS''': Configured DFlash Corrected Wait States (Includes cycles for DFlash access cycles and ECC correction latency)

== CPU Subsystem ==
[[File:TC3xx Processor Core, Local Memory and Connectivity.png|alt=TC3xx Processor Core, Local Memory and Connectivity|thumb|Processor Core, Local Memory and Connectivity]]The Infineon AURIX™ TC3xx features up to 6 processor cores (CPU0 ... CPU5) implementing the [[TriCore Instruction Set Architecture|TC1.6.2 instruction set architecture]]. The following section focuses on the microarchitectural details of the CPU subsystem. For more information about the ISA, please take a look at the [[TriCore Instruction Set Architecture]].

The processor core connects to the following memories and bus interfaces (where implemented):
*Program Scratch-Pad SRAM (PSPR)
*Data Scratch-Pad SRAM (DSPR)
*Program Cache (PCache)
*Data Cache (DCache)
*Local Memory Unit (DLMU)
*Local Pflash bank (LPB)
*SRI slave interface (x2)
*SRI master Interface
*SPB master interface

=== TC1.6.2P Implementation Features ===
*Most instructions executed in 1 cycle
*Branch instructions in 1, 2 or 3 cycles (using dynamic branch prediction)
*Wide memory interface for fast context switch
* Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
*Six memory protection register sets
*Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
*Third pipeline for loop instruction only (zero overhead loop)
*Single precision Floating Point Unit (IEEE-754 Compatible)
*Dedicated Integer divide unit
*18 data memory protection ranges, 10 code memory protection ranges arranged in 6 sets

=== Superscalar Architecture ===
The processor core within the AURIX™ TC3xx family, specifically the TC1.6.2P implementation, employs a superscalar architecture characterized by three parallel pipelines: the Integer Pipeline, the Load/Store Pipeline, and the Loop Pipeline. Superscalar execution is a form of instruction-level parallelism that enables the processor to issue and execute multiple instructions during a single clock cycle. The TriCore™ TC3xx core's superscalar architecture allows it to issue and execute multiple instructions in parallel. Specifically, it can issue up to two instructions simultaneously to the Integer and Load/Store pipelines. However, there are certain constraints on this dual issuing capability. For example, back-to-back data arithmetic instructions can only be issued in separate cycles, and a load/store instruction can be issued either on its own or paired with a data arithmetic instruction, provided the load/store instruction is the second in the pair. Under ideal conditions, with careful instruction scheduling, this dual-issue capability can lead to a throughput of close to 0.5 clock cycles per instruction, effectively executing two instructions per cycle.

=== Pipeline Stages ===
The execution of instructions within the TriCore™ TC3xx core is managed through a pipeline consisting of several stages. In one document it is mentioned that the pipeline consists of 6 stages <ref name="ref3635926" />, but the exact stages remain unclear. From the architecture the following stages can be inferred:

* '''Fetch Stage''': The initial stage in the pipeline is the Fetch stage, where instructions are retrieved from memory. This task is handled by the Instruction Fetch Unit (IFU), which is responsible for fetching instructions from the memory system. To improve efficiency, the IFU employs a pre-fetching mechanism, anticipating the instructions that will be needed and bringing them into the processor before they are actually required. Instructions are fetched through a 64-bit wide Program Memory Interface (PMI), allowing for the retrieval of a significant amount of instruction data in each cycle. The fetched instructions are then placed into an issue FIFO, a buffer capable of holding up to six instructions. This buffer plays a crucial role in managing the flow of instructions to the subsequent execution pipelines. The 64-bit fetch width and the instruction buffer are indicative of a design that aims to ensure a continuous supply of instructions to the pipelines, preventing them from being starved of work. A wider fetch path allows for more instruction bits to be obtained from memory in each clock cycle, while the buffer helps to mitigate temporary delays in instruction fetching.
* '''Execution Unit''': The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop Pipeline. All three pipelines operate in parallel and are capable of executing instructions simultaneously. Each pipline has its own decode stage and two execute stages. Furthermore, the TC3xx features a Floating Point Unit (FPU). It is not clear whether the FPU is part of the execution unit or a separate unit. It is assumed that the FPU also has its own decode stage and an unknown number of execute stages
** '''Decode Stage''': Following the Fetch stage, the instruction are issued to one of the pipelines. In the decode stage of each pipeline, the instruction is examined and translated to determine the specific operation it represents and to identify the operands it will operate on. It is assumed that operands are read from the register file during the decode stage.
** '''Execute Stage''': The Execute stage is where the actual operation specified by the instruction is carried out. Pipeline hazards (stalls) are minimised by the use of forwarding paths between pipeline stages allowing the results of one instruction to be used by a following instruction as soon as the result becomes available.
** '''Writeback Stage''': The final stage in the pipeline is the Writeback stage. In this stage, the results produced by the executed instruction are written back to the processor's register file, making them available for subsequent instructions. It is unclear whether the writeback stage is part of the (two) execution stages or a separate stage.

=== Execution Pipelines ===
The TriCore™ TC3xx core leverages four parallel pipelines to enhance its performance. Each pipeline is designed to handle a specific class of instructions:

* '''Integer Pipeline:''' This pipeline is responsible for executing integer arithmetic and logical instructions, including data-conditional jump instructions, bit manipulation operations, as well as division and multiply-accumulate (MAC) instructions.
* '''Load/Store Pipeline:''' The primary function of this pipeline is to manage memory access operations, including loading data from memory and storing data to memory. It also handles address arithmetic, unconditional jump instructions, procedure call instructions, context-switching operations, and control flow related to context save areas (CSAs).
* '''Loop Pipeline:''' This is a specialized pipeline designed to facilitate zero-overhead loops, a technique that significantly improves the performance of iterative code sections. Its design aims to eliminate or minimize the overhead typically associated with loop control, such as incrementing counters and checking loop conditions. Some documentation suggests that the loop pipeline comes along with a "Loop Cache". This dedicated cache would likely be used to store instructions belonging to the loop, enabling very fast access and execution for repeated iterations.
* '''Floating Point Unit (FPU):''' The FPU is responsible for executing floating-point arithmetic operations

=== Store Buffers ===
The TriCore™ TC3xx core include '''Store Buffers''' to decouple memory write operations from CPU instruction execution. All stores from the Load/Store Pipeline are placed in the store buffer prior to being written to local memory or transferred via the bus system. Write data is taken from the store buffers and written to memory when the target memory or bus interface becomes available. In normal operation the CPU will prioritise memory load operations over store operations in order to improve performance unless the store buffer is full or the order of load and store operations must be preserved (e.g. peripheral space access). The store buffer can hold the data for up to 6 stores operations. To improve performance the store buffer will merge consecutive byte, half-word, and word writes of the same location to reduce the number of memory accesses required.

=== Instruction Timing ===

==Functional Safety and Security Features==
===Hardware Security Module and Encryption===
One of the defining features of the AURIX™ TC3xx family is its robust hardware-based security subsystem, implemented to protect against cyber threats and unauthorized manipulation of vehicle systems. Each TC3xx MCU includes a dedicated ''Hardware Security Module'' (HSM), which is essentially an on-chip co-processor with its own CPU and cryptographic engine designed to handle secure operations. In the second-generation AURIX™ (TC3xx), the HSM was upgraded with support for asymmetric cryptography (e.g., RSA, ECC algorithms) in hardware, providing significantly faster public-key encryption and authentication capabilities than pure software implementations. This HSM supports '''EVITA Full''' (the highest level of the EU’s EVITA automotive security requirements), meaning it can perform secure boot, message authentication, and encryption at a level suitable for protecting critical in-vehicle communications. For example, the HSM can encrypt and authenticate CAN/Ethernet messages to prevent spoofing or tampering on the vehicle network, and it can manage cryptographic keys securely isolated from the main application cores.<ref name="ref14281090104">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref2022357806" />

The security module enables features like '''secure boot''', where the AURIX™ will only execute firmware that is digitally signed by the vehicle manufacturer, thereby preventing unauthorized or malicious code. It also facilitates ''over-the-air (OTA) updates'' in a secure manner: the TC3xx HSM can verify and decrypt update packages received via telematics, allowing firmware upgrades while protecting against attackers attempting to hijack the software. In addition, the HSM includes a true random number generator and supports protocols for immobilizer and theft protection systems. Infineon’s implementation essentially treats the HSM as an “embedded smart card” inside the microcontroller. This approach, building on Infineon’s expertise in chip card security, helps to safeguard sensitive assets like cryptographic keys and to perform secure operations (encryption, decryption, authentication) in hardware, making attacks significantly more difficult. The strong cybersecurity provisions of the AURIX™ TC3xx have made it a preferred choice for vehicle gateway ECUs and central body controllers, which are points of entry for connected car communications and thus high-value targets for hackers. By incorporating the HSM, automotive OEMs can implement advanced security features such as encrypted onboard communication (to thwart bus tampering) and secure diagnostics, ensuring the vehicle’s electronic data is protected against cyber threats even as cars become more connected.<ref name="ref14281090104" /><ref name="ref5727814513">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref><ref name="ref19484776953">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
=== Functional Safety and Fault Tolerance===
Beyond cybersecurity, the AURIX™ TC3xx architecture is built with extensive ''functional safety'' features to meet the highest safety integrity levels in automotive systems. The multi-core design supports ''lockstep operation'', where redundant checker cores run in parallel with main cores and continuously compare results cycle-by-cycle. In TC3xx devices, up to four of the six TriCore™ CPUs have such lockstep partner cores, allowing the microcontroller to detect any single-point CPU failure instantly (if a discrepancy arises between the core and its checker, a fault is signaled). A ''Safety Management Unit (SMU)'' is integrated on-chip to monitor various fault conditions throughout the device – it aggregates error signals from the lockstep cores, memory ECC monitors, clock/watchdog monitors, and peripheral self-tests, and can initiate safe-state actions (like resetting the chip or signaling an error pin to an external supervisor) if a critical fault is detected. The AURIX™ safety concept also includes a distributed Memory Protection Unit (MPU) arrangement, with multiple memory protection contexts that prevent errant or malicious code from writing to wrong memory areas. This helps contain faults and eases the integration of software with mixed criticality (Infineon allows partitioning software components of different ASIL levels on the same MCU while keeping them isolated).<ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref19519075552">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref>

Crucially, the TC3xx family was developed according to ISO 26262 processes and can achieve '''ASIL-D''' (Automotive Safety Integrity Level D), the highest grade for automotive functional safety. Compared to a traditional dual-core lockstep approach, the AURIX’s™ multi-core safety architecture allowed Infineon to reduce certain safety development overheads (earlier Infineon data suggested up to 30% reduction in safety software workload) by providing built-in safety mechanisms and diagnostics. Infineon supplies a comprehensive safety manual and diagnostic libraries for the AURIX™, helping engineers utilize features like CPU self-tests, RAM tests, and CRC checks to comply with safety standards. In addition to automotive standards, the AURIX™ TC3xx has also been qualified for '''industrial safety''': in 2023, Infineon announced support for IEC 61508 metrics, enabling designs with AURIX™ to reach SIL-2 and SIL-3 safety integrity levels for industrial applications. This cross-industry safety compliance is facilitated by the MCU’s redundant design and detailed failure mode documentation (FMEDA) provided by Infineon. In summary, the AURIX™ TC3xx integrates both proactive safety (fault prevention via lockstep, monitoring and protection) and reactive safety (fault detection and safe shutdown), making it a dependable component for systems that cannot afford unintended behavior, whether in cars, factories, or aerospace. <ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref4967712052">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref><ref name="ref196858272">MCUs support industrial functional safety - Electronic Products https://www.electronicproducts.com/mcus-support-industrial-functional-safety/</ref>
== Platform Devices ==
The following table shows a feature overview of the AURIX™ TC3xx Platform family focusing on memory and number of cores.
{| class="wikitable"
!
!Feature
!TC33x
!TC33xEXT
!TC35x
!TC36x
!TC37x
!TC37xEXT
!TC38x
!TC39x
|-
| rowspan="2" |CPUs
|Cores / Checker Cores
|1 / 1
|2 / 1
|3 / 2
|2 / 2
|3 / 2
|3 / 3
|4 / 2
|6 / 4
|-
|Max. Freq.
| colspan="8" |300 MHz
|-
| rowspan="2" |Cache per CPU
|Program [KB]
| colspan="8" |32
|-
|Data [KB]
| colspan="8" |16
|-
| rowspan="3" |SRAM per CPU
|PSPR [KB]
|8
|{{rev|32|CPU0}}
{{rev|64|other}}
|64
|32
|64
|64
|64
|64
|-
|DSPR [KB]
|192
|{{rev|192|CPU0}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|192
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|-
|DLMU [KB]
|8
|{{rev|8|CPU0}}
{{rev|64|other}}
|64
|64
|64
|64
|64
|64
|-
| rowspan="2" |SRAM global
|LMU [KB]
| -
| -
|512
| -
| -
| -
|128
|768
|-
|DAM [KB]
| -
| -
|32
| -
|64
|64
|128
|128
|-
| rowspan="3" |Extension Memory (EMEM)
|TCM [MB]
| -
|1
|2
| -
| -
|2
| -
|2
|-
|XCM [MB]
| -
| -
| -
| -
| -
|1
| -
|2
|-
|XTM [KB]
| -
|16
|16
| -
| -
|16
| -
|16
|-
| rowspan="2" |Program Flash
|Size [MB]
|2
|4
|4
|4
|6
|10
|10
|16
|-
|Banks [MB]
|1 x 2
|2 x 2
|2 x 2
|2 x 2
|2 x 3
|3 x 3, 1 x 1
|3 x 3, 1 x 1
|5 x 3, 1 x 1
|-
| rowspan="2" |Data Flash
|DF0 Size (single-ended) [KB]
|128
|128
|128
|128
|256
|512
|512
|1024
|-
|DF1 Size (single-ended) [KB]
|128
|128
|128
|128
|128
|128
|128
|128
|-
| rowspan="3" |DMA
|Channels
|64
|64
|64
|64
|128
|128
|128
|128
|-
|Move Engines
|2
|2
|2
|2
|2
|2
|2
|2
|-
|Resource Partitions
|4
|4
|4
|4
|4
|4
|4
|4
|}

== Compilers ==
The AURIX™ TC3xx family is a series of high-performance microcontrollers widely used in automotive and industrial applications. Compilers for the AURIX™ TC3xx are crucial for developers aiming to optimize performance, reliability, and safety in their applications. One significant aspect of the compiler landscape for AURIX™ TC3xx is the limited direct support from mainline open-source compilers such as GCC or LLVM/Clang. The primary reason for this is the stringent requirements for functional safety in automotive and industrial applications, which demand specialized features and compliance with safety standards that are often not met by general-purpose open-source compilers.

=== Commercial Compilers ===

# '''Tasking''': Tasking compilers are renowned for their robust support for automotive applications, offering advanced debugging capabilities and optimization techniques tailored for the AURIX™ architecture. They provide extensive code optimization, comprehensive debugging tools, and strong support for safety standards such as ISO 26262, making them ideal for developing high-performance, reliable, and safe applications.
# '''HighTec''': The HighTec compiler is a popular choice, known for its Eclipse-based development environment and strong multicore support. HighTec provides both GCC and LLVM-based ports of open-source compilers tailored specifically for the AURIX™ TC3xx family. These compilers offer efficient parallel execution, advanced code analysis, and an integrated development environment, ensuring robust performance and compliance with safety standards.
# '''Green Hills Software''': Green Hills Software provides a highly optimized toolchain aimed at safety-critical applications, focusing on high performance and strict compliance with automotive standards. Their compiler offers superior optimization, extensive safety features, and a proprietary IDE with specialized tools for automotive development, ensuring developers can meet the stringent demands of functional safety.

=== GCC for AURIX™ ===

While mainline GCC does not directly support the AURIX™ TC3xx family, there is an unofficial GCC version available for AURIX™. Due to the GNU General Public License (GPL), the source code from HighTec was retrieved and, along with binary versions, published on GitHub:

*GCC 4.9.4/Binutils 2.20/Newlib 1.18 for Tricore™ AURIX™ [[https://github.com/volumit/package_494 Source]] [[https://github.com/volumit/tricore_gcc494_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc494_linux_bins Prebuild Linux Binaries]]
*GCC 9.4.0/Binutils 2.20/Newlib 1.18 for Tricore™ AURIX™ [[https://github.com/volumit/package_940 Source]] [[https://github.com/volumit/tricore_gcc940_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc940_linux_bins Prebuild Linux Binaries]]
*GDB 10.0.50 for Tricore™ AURIX™ [[https://github.com/volumit/gdb-tricore Source]]
==emmtrix Tools for AURIX™ TC3xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX™ TC3xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===
====Architecture & Variant Consulting====
* Support in selecting suitable AURIX derivatives for new product generations (trade-offs between performance, price, safety, and peripheral features)
*Analysis of requirements and mapping to specific AURIX product families (e.g., TC3xx vs. TC4xx)
*Analysis/identification of performance margins for down- or upgrades
==== Runtime Analysis & Performance Engineering ====
* Execution of detailed runtime analyses (maximum/minimum vs. average)
* Identification of bottlenecks in program execution, including benchmarking
*Optimization of access to flash, RAM, and peripherals (e.g., cache configuration, DMA utilization)
====Dependency Analysis====
*Freedom from interference (ASIL level check)
====Multicore Design & Scheduling Concepts ====*Development of core mapping strategies (static vs. dynamic assignment of compute-intensive tasks)
*Support for integrating bare-metal scheduling on AURIX
*Assistance with architectural decisions to meet functional safety requirements in multicore systems
====Training & Know-how Transfer====*Technical in-house workshops on AURIX optimization, multicore strategies
*Coaching of employees/project teams in performance analysis and systematic tuning
==See Also==

*[[Infineon AURIX TC4x|Infineon AURIX™ TC4x]]
*[[Infineon AURIX TC2xx|Infineon AURIX™ TC2xx]]
*[[TriCore Instruction Set Architecture]]

==External Links==

*https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/
*[https://documentation.infineon.com/aurixtc3xx/docs/qmd1702366622648 AURIX™ TC3xx user manuals]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d3605221d96 AURIX™ TC3xx User Manual Part-1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d35f8541d94 AURIX™ TC3xx User Manual Part-2]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd AURIX™ TC3xx Architecture vol 1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 AURIX™ TC3xx Architecture vol 2]

== References ==
<references />
[[Category:Supported Architectures]]

{{#seo:
|title=Infineon AURIX TC3xx Family – Deep Dive
|description=This deep dive into Infineon's AURIX TC3xx family explores its multi-core TriCore architecture, real-time capabilities, safety and security features and tools
|image=File:AURIX_TC399_LFBGA-516_plain.jpg
|keywords=AURIX, Infineon, TC3xx, microcontroller, TriCore, automotive, ADAS, ISO 26262, functional safety, embedded security, ASIL-D, deep dive
}}

Infineon AURIX TC2xx

2025-05-21T08:14:08Z

Mira.steinmetz:

'''Infineon AURIX™ TC2xx''' is a family of 32-bit automotive microcontrollers developed by Infineon Technologies. ''AURIX™'' stands for ''“Automotive Realtime Integrated Next Generation Architecture”'', reflecting its design for real-time, safety-critical automotive applications<ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. The TC2xx series (first-generation AURIX™) is based on a multicore architecture featuring up to three independent 32-bit '''TriCore™''' processor cores. Introduced around 2012, the AURIX™ TC2xx marked Infineon’s transition to a multicore microcontroller platform (fabricated in 65 nm technology) after earlier single-core TriCore™ generations. It was designed from the ground up to meet stringent automotive safety requirements (ISO 26262) and to provide higher performance and integration for applications like engine management, chassis control, and driver assistance systems.<ref name="ref1222155140" /><ref name="ref1490396573">Optimized for Success - EE Times Europe https://www.eetimes.eu/optimized-for-success/</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>

The AURIX™ TC2xx family’s design philosophy is to combine '''safety''', '''security''', and '''performance''' in one scalable MCU platform. It achieves high functional safety compliance (up to '''ASIL-D''', the highest automotive safety integrity level) with less development effort compared to traditional dual-controller lockstep systems<ref name="ref572781451" />. Infineon claims that using AURIX™ can cut safety-related development time by ~30% versus classical lockstep architectures, thanks to its built-in fault detection and monitoring hardware. At the same time, the TC2xx provides significant performance headroom – roughly 50% to 100% higher computational performance compared to its predecessors – while maintaining power consumption similar to previous single-core designs. To address emerging automotive security needs, the AURIX™ MCUs also integrate a dedicated Hardware Security Module ('''HSM''') on-chip, which protects against IP theft, fraud, and tampering. This combination of features makes the AURIX™ TC2xx a popular choice for consolidating various automotive control functions (powertrain, safety, body, etc.) onto one platform, without sacrificing reliability or efficiency.<ref name="ref572781451" /><ref name="ref71179009">32-bit TriCore™ AURIX™– TC2xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/</ref>
==Architecture==
The AURIX™ TC2xx is built on Infineon’s '''TriCore™''' architecture, which uniquely unifies traits of a RISC processor, a microcontroller, and a DSP (digital signal processor) into one core design. Each TriCore™ CPU in the TC2xx is a 32-bit superscalar processor that supports both 32-bit and 16-bit instruction formats (the latter for code size efficiency). The TriCore™ instruction set architecture includes typical RISC features (load/store architecture, 4 GB address space) and DSP capabilities (such as multiply-accumulate instructions and bit manipulation) in a single core. The cores also have an optional floating-point unit (FPU) and support SIMD (single-instruction multiple-data) operations for signal processing acceleration. The maximum core frequency in the TC2xx family is 300 MHz, and devices achieve about 1.7–2.4 DMIPS/MHz per core, providing robust real-time performance.<ref name="ref1222155140" /><ref name="ref71179009" />

In terms of core configuration, high-end AURIX™ TC2xx models implement three main TriCore™ CPUs, which can be run in parallel or in redundant (lockstep) pairs for safety. Some variants include a redundant checker core that shadows a primary core to detect calculation errors (a technique to meet SIL/ASIL safety goals). The multicore architecture is supported by a layered memory system: each TriCore™ has tightly coupled local memory for fast instruction and data access, and they share access to large on-chip Flash and RAM via an internal bus matrix. Memory options in the TC2xx range from about '''0.5 MB up to 8 MB of on-chip Flash''', and from ~50 KB up to 2.7 MB of SRAM, depending on the specific device. This on-chip memory (with ECC protection on memories for safety) allows real-time code execution and data storage without external memory in most use cases. For peripherals and I/O, the AURIX™ architecture includes a rich set of on-chip modules connected via internal buses, such as analog-to-digital converters, timer units, communication interfaces, and direct memory access (DMA) controllers. AURIX™ TC2xx MCUs typically provide interfaces like multiple CAN/CAN-FD channels, LIN/UART, SPI, I²C, Ethernet (on higher-end models), and automotive-specific buses (e.g. FlexRay on some variants), making the chip a self-contained controller for complex automotive networks.'''<ref name="ref572781451" />'''<ref name="ref71179009" /><ref name="ref957370148">Infineon TriCore - Wikipedia https://en.wikipedia.org/wiki/Infineon_TriCore</ref>

The '''Generic Timer Module (GTM)''' is a notable part of the AURIX™ TC2xx architecture. It is a sophisticated timer/co-processor integrated on-chip to handle complex timing, PWM generation, input capture, and other signal conditioning tasks across more than 200 channels. There are also specialized accelerators and co-processors on certain TC2xx devices, such as a '''Hardware Fast Fourier Transform (HFFT)''' unit for signal processing and a '''Parallel Pixel Processor''' for simple video or sensor data processing. These dedicated engines offload the TriCore™ CPUs for specific high-load tasks (e.g. radar signal FFTs or encoder signal processing), improving overall throughput in automotive applications. The AURIX™ architecture uses a single-power supply (5V or 3.3V) design and includes an on-chip voltage regulator (EVR), simplifying power management. The MCUs are offered in a variety of package types (from compact QFP-64 up to large BGA-516) to accommodate different I/O needs. Overall, the TC2xx architecture is highly integrated and optimized for real-time, combining multiple CPU cores with ample flash memory, SRAM, and peripherals on one chip to serve as a '''central control unit''' in vehicles.<ref name="ref1222155140" /><ref>AURIX™ Unleashed - RS Components https://docs.rs-online.com/0f3f/0900766b815c315c.pdf</ref>
====CPU access latency (TC29x) ====
{| class="wikitable"
!CPU Access Type!!Local CPU
|-
|Data read access to own DSPR||0
|-
|Data write access to own DSPR||0
|-
|Data read access to own or other PSPR||8
|-
|Data write access to own or other PSPR||0
|-
|Data read access to other DSPR||8
|-
|Data write access to other DSPR||0
|-
|Instruction fetch from own PSPR
|0
|-
|Instruction fetch from other PSPR (critical word)||8
|-
|Instruction fetch from other PSPR (any remaining words)||0
|-
|Instruction fetch from other DSPR (critical word)||8
|-
|Instruction fetch from other DSPR (any remaining words)||0
|-
|Initial Pflash Access (critical word)||7 + configured PFlash Wait States
|-
|Initial Pflash Access (remaining words)||0
|-
|PMU PFlash Buffer Hit (critical word)||6
|-
|PMU PFlash Buffer Hit (remaining words)||0
|-
|Initial Dflash Access||7 + configured DFlash Wait States
|-
|TC1.6P Data read from System Peripheral Bus (SPB)
|{{rev|4|2=fCPU = fSPB}} {{rev|7|2=fCPU = 2*fSPB}} {{rev|10|2=fCPU = 3*fSPB}}
|-
|TC1.6P Data write to System Peripheral Bus (SPB)||0
|}
*

==Key Features==

* '''Safety Mechanisms:''' The AURIX™ TC2xx was developed via an ISO 26262-compliant process and includes multiple hardware mechanisms to achieve '''functional safety up to ASIL-D'''. Notably, it supports ''lockstep'' operation, where one or two of the TriCore™ CPUs can run in redundant lockstep mode with another core to detect discrepancies (faults) cycle-by-cycle. A Safety Management Unit ('''SMU''') is built in to monitor critical system parameters and handle faults. The architecture employs memory protection units and safe internal communication buses to isolate and supervise different software domains. Other safety features include '''error-correcting code (ECC)''' on flash and RAM, redundant peripherals (for example, duplicated ADC channels), watchdog timers, clock and voltage monitors, and self-test routines. These features allow developers to more easily implement safety-critical functions and meet standards like IEC 61508 (SIL-3) or ISO 26262 (ASIL-D) using a single AURIX™ MCU, whereas achieving the same on a traditional single-core MCU might require additional external safety ICs or companion processors.<ref name="ref1490396573" /><ref name="ref572781451" />
* '''Security Functions:''' Infineon integrated a dedicated Hardware Security Module ('''HSM''') into the AURIX™ TC2xx family to address automotive cybersecurity requirements. This HSM is essentially an on-chip co-processor (with its own CPU and flash) that handles cryptographic operations and secure key storage isolated from the main cores. It follows the EVITA (E-safety Vehicle Intrusion Protected Applications) guidelines for automotive security. The HSM enables features like secure boot, encryption/decryption, authentication, and detection of software tampering. By having a built-in “embedded smart card” for security, the AURIX™ can implement anti-theft, anti-cloning, and secure onboard communication measures without needing an external security chip. This integration is a key differentiator, as it helps protect vehicle functions (e.g. immobilizers, firmware updates, V2X communication) against hacking and unauthorized modifications.<ref name="ref1222155140" /><ref name="ref71179009" />
* '''Performance and DSP Capability:''' Each TriCore™ CPU in the TC2xx is capable of up to 300 MHz operation, and combined the multicore setup offers considerable processing power for an MCU (Infineon cites up to ~1.8 GFLOPS of DSP throughput for the highest models). The TriCore™ design delivers around '''1.7–2.4 DMIPS/MHz''' per core, meaning a triple-core AURIX™ at max frequency can exceed 2000 DMIPS of total throughput. The inclusion of DSP instructions and dedicated accelerators enables the AURIX™ to handle computationally intensive tasks (like control algorithms, filtering operations, or even rudimentary neural networks) that previously might require a separate DSP or FPGA. A built-in '''Floating Point Unit''' on each core supports single-precision (and optional double-precision in some cases) arithmetic, beneficial for model-based control algorithms and automotive sensor processing. Peripherals like the '''Generic Timer Module (GTM)''' and '''Hardware FFT''' accelerator (available on select TC2xx variants) further boost real-time performance for handling high-frequency events (e.g. engine ignition timing, motor control PWM, radar signal analysis) without overloading the CPU. Despite the performance, the TC2xx was designed with efficiency in mind; Infineon managed to double the performance over the prior generation (TC1xx AUDO) while keeping power consumption at comparable levels. The MCUs also support various low-power modes and a standby controller to minimize energy usage when parts of the system are idle.<ref name="ref1222155140" /><ref name="ref572781451" />
* '''Power and Integration:''' As a system-on-chip for vehicles, AURIX™ TC2xx integrates a wide range of '''communication interfaces''' and analog/digital peripherals. Common features include multiple CAN bus controllers (often with CAN FD support), LIN/UART, SPI and I²C channels, FlexRay communication in high-end models, and even Ethernet (in variants aimed at gateway or ADAS roles). High-resolution '''ADC units''' (with shared and redundant channels) allow precise sensor measurements for engine or chassis control. There are also specialized modules like delta-sigma ADCs and SENT interfaces for automotive sensor inputs. This rich peripheral set reduces the need for external components, helping to lower the overall system Bill of Materials. The TC2xx devices operate over a broad temperature range (typically –40 °C to +150 °C), meeting the demands of under-the-hood automotive environments. They run from a single supply (with internal regulators), simplifying designs, and support both 5 V and 3.3 V systems for compatibility with a variety of sensors and actuators. Combined with its safety and security features, the AURIX’s™ high integration makes it a one-chip solution for many complex embedded applications.<ref name="ref1222155140" /><ref name="ref1490396573" /><ref name="ref71179009" /><ref name="ref957370148" />

==Applications==
The Infineon AURIX™ TC2xx family is primarily targeted at the '''automotive industry''', especially domains requiring high reliability and real-time control. Its initial use cases were in '''powertrain''' and engine management systems – for example, controlling combustion engines, managing fuel injection and ignition, and coordinating electric motor and battery systems in hybrid or electric vehicles. The multi-core AURIX™ can run multiple control algorithms in parallel (e.g. for an engine’s cylinders, transmission and motor inverter concurrently), which is valuable in modern electrified powertrains. Beyond engines, AURIX™ TC2xx MCUs are used in '''chassis and safety systems''': they can serve as the central controller for '''anti-lock braking systems (ABS)''' and stability control, '''airbag control units''', '''electric power steering (EPS)''' systems, and suspension controllers. Advanced Driver Assistance Systems ('''ADAS''') and autonomous driving modules in earlier generations of vehicles have also employed AURIX™ for tasks such as sensor fusion, radar signal processing, and acting as a safety supervisor for driving assistance features<ref name="ref572781451" />. For example, a radar unit for adaptive cruise control might use an AURIX™ to perform real-time signal processing (using its DSP capabilities and HFFT) and make high-level decisions, all within an ASIL-D safe environment.<ref name="ref572781451" /><ref name="ref1228701036">https://resources.tasking.com/sites/default/files/2021-02/Take%20Advantage%20of%20Infineon%20AURIX%20TC3xx%20Family%20With%20the%20Right%20Compiler_WEB.pdf</ref>

Thanks to its safety certification and robust design, the AURIX™ TC2xx has seen adoption in any application that cannot tolerate failure. This includes '''industrial automation and robotics''', where the MCU’s reliability and support for functional safety (IEC 61508) are attractive. In industrial motor drives or robotics controllers, an AURIX™ might handle precise motor control algorithms and system monitoring. Other use cases outside pure automotive include '''commercial vehicles and transportation''' (trucks, agricultural and construction machinery), which have similar safety and durability requirements. The AURIX’s™ extensive communication interfaces also make it suitable as a gateway or central node in complex networks – for instance, acting as a domain controller in modern automotive E/E architectures to coordinate data between powertrain, body, and ADAS subsystems. Some '''electric vehicle (EV)''' platforms use AURIX™ MCUs in battery management systems and inverter controls, leveraging its calculation power for battery algorithms and its safety for monitoring cell health. In summary, the TC2xx family finds use in scenarios that demand '''real-time performance with high safety integrity''', predominantly in automotive (engine, transmission, chassis, safety, ADAS) but also in high-end industrial embedded systems.<ref name="ref71179009" /><ref name="ref1228701036" />

==emmtrix Tools for AURIX™ TC2xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX™ TC2xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ TC2xx / [[Infineon AURIX TC3xx|TC3xx]]/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

==== Architecture & Variant Consulting ====

* Support in selecting suitable AURIX derivatives for new product generations (trade-offs between performance, price, safety, and peripheral features)
* Analysis of requirements and mapping to specific AURIX product families (e.g., TC3xx vs. TC4xx)
* Analysis/identification of performance margins for down- or upgrades

==== Runtime Analysis & Performance Engineering ====

* Execution of detailed runtime analyses (maximum/minimum vs. average)
* Identification of bottlenecks in program execution, including benchmarking
* Optimization of access to flash, RAM, and peripherals (e.g., cache configuration, DMA utilization)

==== Dependency Analysis ====

* Freedom from interference (ASIL level check)

==== Multicore Design & Scheduling Concepts ====

* Development of core mapping strategies (static vs. dynamic assignment of compute-intensive tasks)
* Support for integrating bare-metal scheduling on AURIX
* Assistance with architectural decisions to meet functional safety requirements in multicore systems

==== Training & Know-how Transfer ====

* Technical in-house workshops on AURIX optimization, multicore strategies
* Coaching of employees/project teams in performance analysis and systematic tuning

== See Also ==

* [[Infineon AURIX TC3xx|Infineon AURIX™ TC3xx]]
* [[Infineon AURIX TC4x|Infineon AURIX™ TC4x]]
* [[TriCore Instruction Set Architecture|TriCore™ Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/
* [https://www.infineon.com/dgdl/Infineon-TC29x_B-step-UM-v01_03-EN.pdf?fileId=5546d46269bda8df0169ca1bdee424a2 TC29x B-Step User Manual]

== References ==
<references />
[[Category:Supported Architectures]]

Infineon AURIX TC3xx

2025-04-08T08:39:17Z

Mira.steinmetz:

[[File:AURIX TC399 LFBGA-516 plain.jpg|thumb|Infineon AURIX™ TC3xx second-generation microcontroller (TC399 BGA package). The AURIX™ TC3xx family integrates multiple TriCore™ CPUs and on-chip safety/security modules for automotive applications.|alt=TC399 BGA package]]
The '''Infineon AURIX™ TC3xx''' (Automotive Realtime Integrated neXt-generation architecture) is a family of 32-bit automotive microcontrollers introduced as the second generation of Infineon’s AURIX™ platform. Launched in 2016 as a successor to the earlier [[Infineon AURIX TC2xx|AURIX™ TC2xx series]], the TC3xx devices emphasize high performance, functional safety, and embedded security for advanced automotive and industrial applications. AURIX™ TC3xx microcontrollers feature a hexa-core [[TriCore Instruction Set Architecture|''TriCore'' processor architecture]] with enhanced safety measures, making them well-suited for demanding tasks such as autonomous driving domain controllers, powertrain control, and sensor data fusion in advanced driver-assistance systems (ADAS). The combination of multiple CPU cores, extensive on-chip memory, and a rich peripheral set allows TC3xx chips to deliver real-time responsiveness and reliability in safety-critical environments while meeting stringent automotive standards (such as ISO 26262 for functional safety).<ref name="ref1951907555">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref><ref name="ref1428109010">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref1948477695">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
==Applications==
AURIX™ TC3xx microcontrollers are used in a variety of safety-critical and high-performance applications across the automotive and industrial sectors. Key application domains include:
*'''Automotive Systems:''' The TC3xx family was primarily designed for automotive use and finds broad application in vehicles’ electronic control units (ECUs). Notably, it is used in ''powertrain and drivetrain control'' (engine management, transmission control, hybrid/electric vehicle inverter control, battery management) where its real-time processing and resilience support precise actuator control. It is also deployed in ''chassis and safety systems'' such as anti-lock braking systems (ABS), electronic stability control, airbag controllers, and electric power steering, leveraging its redundancy and fast response for fail-safe operation. With the growth of ADAS and autonomous driving, AURIX™ TC3xx devices serve as domain controllers for ''ADAS sensor fusion'', handling data from radar, LiDAR, camera, and ultrasonic sensors and performing environment modeling and decision-making algorithms. Their combination of multiple cores and a built-in radar signal processing sub-system makes them an attractive choice for tasks like front radar processing, sensor fusion hubs, and ''autonomous driving domain controllers'' that must meet ASIL-D safety levels.<ref name="ref14281090102">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
*'''Industrial Automation and Robotics:''' Infineon has also positioned the AURIX™ family for use in industrial applications that demand high reliability. The TC3xx MCUs, with their hardware self-test mechanisms and safety documentation, can be found in ''industrial motor drives, robotics controllers, and PLCs (programmable logic controllers)'', where they help achieve functional safety certifications up to SIL-3 (according to IEC 61508). The powerful TriCore™ cores and rich peripheral set enable complex motor control algorithms (e.g., field-oriented control for servo motors) and real-time sensor processing in factory automation. Additionally, the support for automotive-grade networking (CAN/CAN-FD, Ethernet) and timing peripherals makes them suitable for synchronous control in robotics and machinery. Infineon’s provision of AUTOSAR-compatible software for AURIX™ has even facilitated its use in non-automotive settings such as medical devices and elevator controllers, where proven safety and security are required.<ref name="ref496771205">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref>
*'''Aerospace and Defense:''' The high fault-tolerance and deterministic performance of the AURIX™ TC3xx architecture also attract interest for aerospace and other mission-critical uses. In avionics systems or autonomous drones, for instance, the lockstep core configuration and robust error checking of AURIX™ can provide an added layer of reliability for flight control computers or navigation systems. While primarily an automotive chip, its ability to operate in harsh conditions (−40°C to 150°C range) and to detect internal failures in real-time makes it viable for certain aerospace electronic systems. Some defense and aerospace projects leverage COTS (commercial off-the-shelf) automotive components like AURIX™ for applications such as unmanned vehicle control and high-reliability communication links, given its safety pedigree. (In these domains, additional analysis and possibly radiation testing would be performed if the devices are used in high-altitude or space environments.)
== Architecture Overview ==
[[File:Infineon TC3xx Architecture.webp|545x545px|thumb|alt=TC3xx Architecture Overview|TC3xx Architecture Overview]]
=== Processor Cores and Architecture===
The AURIX™ TC3xx family implements Infineon’s TriCore™ architecture, which uniquely combines aspects of RISC microcontrollers, DSP (digital signal processor) capabilities, and conventional microprocessor features into a single core design. Each TC3xx device can include up to six independent TriCore™ 32-bit CPU cores (TriCore™ version 1.6.2), all capable of running at up to 300 MHz clock frequency. Four of these cores can operate in dual-core lockstep pairs (with one core acting as a redundant checker for its partner) to provide fault detection for safety-critical functions. The TriCore™ cores use a superscalar Harvard architecture with 32-bit instruction words (and support for mixed 16/32-bit instruction encoding for code density). Each core includes a dedicated Floating Point Unit (FPU) for single-precision arithmetic and supports DSP-oriented instructions (e.g. single-cycle 16×16 MAC operations, SIMD for 16-bit/8-bit data) to accelerate signal processing tasks. For fast real-time performance, the architecture offers low interrupt latency (with automatic context save on-chip) and features like zero-overhead loops and a programmable peripheral timer unit for scheduling tasks. In total, a high-end TC3xx (such as the TC39x) provides six 300 MHz cores plus four checker cores, yielding a theoretical processing throughput of up to ~2400 DMIPS (Dhrystone MIPS) when all cores are utilized. This represents roughly a threefold increase in computational power over the previous AURIX™ generation (which achieved ~740 DMIPS with three cores).<ref name="ref19484776952">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref><ref name="ref2022357806">UDE Debug, Trace and Test solutions for Infineon TriCore™ AURIX™ TC32, TC33, TC35, TC36, TC37, TC38, TC39, TC3x Microcontrollers https://www.pls-mc.com/products/infineon-tricore-aurix-tc32-tc33-tc35-tc36-tc37-tc38-tc39-microcontrollers/</ref><ref name="ref14281090103">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref>
===Memory Subsystem and Cache===
AURIX™ TC3xx microcontrollers integrate a large on-chip memory system to meet real-time and safety requirements. Program flash memory sizes range up to 16 MB on the largest models, with over 6 MB of on-chip SRAM available for data and scratchpad usage. Each TriCore™ CPU has its own tightly-coupled local memories as well as caches: for example, each core includes a 32 KB instruction cache and a 16 KB data cache. In addition, every core has separate local RAM blocks (Harvard architecture) for instructions and data (often termed PSPR and DSPR – Program Scratch-Pad RAM and Data Scratch-Pad RAM) that allow deterministic access for time-critical routines. Shared global memory is provided via a Local Memory Unit (LMU) which can be up to several hundred kilobytes (for instance, 768 KB in the TC39x) accessible by all cores. The memory system is connected by a high-bandwidth internal bus fabric (the SRI crossbar and peripheral buses) that arbitrates access between cores, DMA engines, and peripherals. This architecture ensures that each core can quickly fetch instructions and data either from its local cache/RAM or the central memory, enabling efficient parallel processing. Memory protection hardware is also built-in to isolate tasks of different criticality, an important feature for safety and security.<ref name="ref19484776952" /><ref name="ref5727814512">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
===Peripherals and Interfaces===
One of the strengths of the AURIX™ TC3xx architecture is its extensive set of on-chip peripherals and interface controllers, designed to handle the complex networking and I/O needs of modern vehicles and industrial systems. Key peripheral features and interfaces include:<ref name="ref19484776952" /><ref name="ref2022357806" /><ref name="ref14281090103" /><ref name="ref3635926">AURIX™ Training System Architecture https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_System_Architecture-Training-v01_00-EN.pdf?fileId=5546d46272e49d2a0172eb476d56739e</ref>

* '''Networking Interfaces:''' Multiple CAN FD controllers (supporting up to 12 CAN-FD channels in high-end variants) for in-vehicle networking, with legacy CAN and LIN interfaces (up to 24 LIN channels) for lower-speed device communication. Many TC3xx devices also integrate up to two FlexRay controllers for time-triggered automotive networks (maintaining compatibility with earlier automotive communication standards). For high-bandwidth data, a Gigabit Ethernet MAC is included, enabling uses like automotive Ethernet (e.g., audio-video bridging and IP-based connectivity).
* '''Analog and Timers:''' A suite of analog peripherals including multiple ADC units for sensor interfacing and motor control, and DACs in some models. Sophisticated timer units are on-chip, notably the Generic Timer Module (GTM) and Capture/Compare Units (CCU6), which can generate complex PWM waveforms and handle events for engine control, power inverters, or robotics with minimal CPU intervention. These timers enable precise control of actuators (e.g. fuel injection timing, electric motor commutation) in real time.
*'''Serial Interfaces:''' SPI, I²C, UART/LIN and other serial interfaces for connecting to external sensors, actuator controllers, and memory. The controllers often support multiple instances (several SPI channels, etc.) to accommodate numerous devices. AURIX™ TC3xx also provides an external bus interface (EBU) for parallel memory or FPGA connectivity, and an SD/MMC interface (eMMC) to connect external flash memory for data logging or over-the-air update storage.
*'''Dedicated Processing Units:''' Some AURIX™ TC3xx models include special accelerators, such as a hardware Fast Fourier Transform unit (HW-FFT) and up to two Signal Processing Units (SPUs) optimized for radar signal processing. These enable the microcontroller to handle radar front-end data or other intensive DSP tasks (like Fourier transforms for radar or audio signals) on-chip, which is crucial for advanced driver assistance sensors. There is also a ''Security Module'' (covered in a later section) and a Safety Management Unit that supervise system integrity.
*'''Other On-chip Modules:''' Watchdog timers, error-correction coders for memories (ECC on flash and RAM for reliability), a programmable interrupt system, multiple DMA channels (up to 128 DMA channels) for efficient data movement, and debug interfaces (JTAG and a 2/3-pin DAP) for development. The on-chip debug system supports tracing of program execution (via a built-in Emulation Memory, MCDS) to aid in complex multicore software development.

Overall, the AURIX™TC3xx provides a highly integrated SoC-like platform, allowing a single chip to manage tasks ranging from powertrain control and chassis control to infotainment gateways. This high level of integration reduces the need for separate companion chips and helps to lower system complexity and cost.
===Performance and Benchmarking===
Fabricated in a 40 nm embedded flash process<ref name="ref2022357806" />, AURIX™ TC3xx processors achieve significant performance gains over prior generations while maintaining automotive-grade power efficiency. With six 32-bit cores at 300 MHz (four of them paired in lockstep), a flagship TC3xx device (e.g., TC39x) can deliver up to approximately 2,400 DMIPS of aggregate computing throughput<ref name="ref2022357806" />. In terms of per-core performance, the TriCore™ architecture yields around 1.3–2.0 DMIPS/MHz depending on the instruction mix, meaning each 300 MHz core can approach ~400–600 DMIPS in optimized scenarios<ref name="ref14281090103" /><ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. This is on par with or exceeding many contemporary 32-bit automotive MCUs. The integrated DSP extensions and optional accelerators (like the FFT unit) also enable high-speed signal processing, with Infineon citing up to ~1.8 GFLOPS of DSP throughput for certain operations<ref name="ref1222155140" />.

Real-world performance improvements of the TC3xx over its predecessor are notable: for example, compared to the first-generation AURIX™ (which offered up to 740 DMIPS), the TC3xx’s expanded core count and clock speed provide roughly three times the computational power on the same type of workload<ref name="ref14281090103" />. This extra headroom allows more functions (such as running multiple control algorithms or sensor fusion tasks in parallel) to be consolidated onto one microcontroller without compromising real-time deadlines<ref name="ref14281090103" />. Despite the increase in speed and core count, the TC3xx family was designed with power and thermal constraints in mind, achieving these gains within similar power consumption envelopes as the previous generation by leveraging the smaller 40 nm process and power-saving features like clock gating<ref name="ref5727814512" />. The deterministic real-time performance (with features like lockstep and tightly-coupled memory) makes the AURIX™ TC3xx suitable for the most demanding automotive applications, where consistent low latency and high throughput are required simultaneously.

== On-Chip System Connectivity and Bridges ==
[[File:TC3xx On-Chip System Connectivity.png|thumb|The TC3xx has two '''SRI Domains''' (SRI0 and SRI1). CPU0 to CPU3 are connected to SRI0, CPU4/5 are connected to SRI1.|alt=TC3xx On-Chip System Connectivity|423x423px]]
The AURIX™ TC3xx Platform has three independent on-chip connectivity resources:

* '''System Resource Interconnect Fabric (SRI Fabric)''' connects the TriCore™ CPUs, the DMA module, and other high bandwidth requestors to high bandwidth memories and other resources for instruction fetches and data accesses. A key component of the fabric is the SRI crossbar, which connects all the agents in one SRI domain. The SRI crossbar carries the transactions between the SRI Masters and SRI Slaves of the domain. The SRI crossbar supports parallel transactions between different SRI Master and SRI Slave agents. In addition to the parallelism of concurrent requests, it also supports pipelined requests from an SRI Master to a SRI Slave.
* '''System Peripheral Bus (SPB)''' connects the TriCore™ CPUs, the DMA module, and other SPB masters to the medium and low bandwidth peripherals. SPB masters do not directly connect to the SRI Fabric, and will access SRI attached resources via a SFI_F2S Bridge.
* '''Back Bone Bus (BBB)''' connects the TriCore™ CPUs, the DMA module, and SPB masters with ADAS resources. SRI Masters do not directly connect to the BBB, but access BBB attached resources via a SFI_S2F Bridge. SPB masters also do not directly connect to the BBB, but access BBB attached resources via bridging over the SRI Fabric.

=== CPU Resource Access Times ===
These tables describe the CPU access times to various resources in CPU clock cycles for the AURIX™ TC3xx Platform. In the case of load or fetch accesses, the access times are the minimum number of CPU stall cycles to complete the access. If there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

For write access, the access times are the maximum for a sequence of such access (non-conflicting). In many cases for a singleton access, or a short sequence, write buffering reduces the stall effect seen by a CPU, sometimes to 0. However, as with loads and fetches, if there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

==== Access latency for global resources ====
{| class="wikitable"
|+
! CPU Access Type !! CPU stall cycles
!Notes
|-
| Data read from System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
| rowspan="2" |The final number of stall cycles will depend on the real number of WS generated by the target resource.
|-
| Data write to System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC39x, TC37xED) || <math>9 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
| rowspan="2" |When SFI_S2F is connected to XBar2 (TC39x and TC37xED) there is an additional latency due to access going through an S2S.
|-
| Data write to Back Bone Bus (BBB) (TC39x, TC37xED) || <math>5 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC35x, TC33xED) || <math>6 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
|
|-
| Data write to Back Bone Bus (BBB) (TC35x, TC33xED) || <math>3 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|
|}


* '''Module Wait State''': The number of wait states for read and for write accesses is >= 1 and depends on the accessed module and its configuration.


==== CPU Accesses: Stall cycles for local and SRI resources ====
{| class="wikitable"
|+
! CPU Access Type !! Local CPU !! Local SRI !! Remote SRI Domain
|-
| Data read from DSPR || 0 || 7 || 10
|-
| Data write to DSPR || 0 || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from DSPR || See local SRI column || 7 || 10
|-
| Data read from DLMU || 0 || 7 || 10
|-
| Data write to DLMU || 2 || 5, {{rev|3|with Pipelining}}|| 5, 4
|-
| Instruction fetch from DLMU || See local SRI column || 7 || 10
|-
| Data read from PSPR || See local SRI column || 7 || 10
|-
| Data write to PSPR || See local SRI column || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from PSPR || 0 || 7 || 10
|-
| Data read from PFlash || 5 + PWS || 10 + PWS || 13 + PWS
|-
| Instruction fetch from PFlash (buffer miss) || 2 + PWS || 9 + PWS || 12 + PWS
|-
| Instruction fetch from PFlash (buffer hit) || 3 || 6 || 9
|-
| Data read from LMU || n.a. || 7 || 10
|-
| Data write to LMU || n.a. || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from LMU || n.a. || 7 || 10
|-
| Data read from DFlash || n.a. || 5 + 3*(3 + DCWS) || 8 + 3*(3 + DCWS)
|-
| Data read access from EMEM (TC39x, TC37xED) || n.a. || n.a. || 14, {{rev|15|fBBB < fSRI}}
|-
| Data write access to EMEM (TC39x, TC37xED) || n.a. || n.a. || 9
|-
| Data read access from EMEM (TC35x, TC33xED) || n.a. || 11, {{rev|12|fBBB < fSRI}}|| n.a.
|-
| Data write access to EMEM (TC35x, TC33xED) || n.a. || 9 || n.a.
|-
| Data read access from DAM || n.a. || 10 || 13
|-
| Data write access to DAM || n.a. || 7 || 7
|}

* '''Remote SRI Domain''': Only applies to products with SRI extenders. Additional latency due to access going through an S2S
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''DCWS''': Configured DFlash Corrected Wait States (Includes cycles for DFlash access cycles and ECC correction latency)

== CPU Subsystem ==
[[File:TC3xx Processor Core, Local Memory and Connectivity.png|alt=TC3xx Processor Core, Local Memory and Connectivity|thumb|Processor Core, Local Memory and Connectivity]]The Infineon AURIX™ TC3xx features up to 6 processor cores (CPU0 ... CPU5) implementing the [[TriCore Instruction Set Architecture|TC1.6.2 instruction set architecture]]. The following section focuses on the microarchitectural details of the CPU subsystem. For more information about the ISA, please take a look at the [[TriCore Instruction Set Architecture]].

The processor core connects to the following memories and bus interfaces (where implemented):
*Program Scratch-Pad SRAM (PSPR)
*Data Scratch-Pad SRAM (DSPR)
*Program Cache (PCache)
*Data Cache (DCache)
*Local Memory Unit (DLMU)
*Local Pflash bank (LPB)
*SRI slave interface (x2)
*SRI master Interface
*SPB master interface

=== TC1.6.2P Implementation Features ===
*Most instructions executed in 1 cycle
*Branch instructions in 1, 2 or 3 cycles (using dynamic branch prediction)
*Wide memory interface for fast context switch
* Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
*Six memory protection register sets
*Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
*Third pipeline for loop instruction only (zero overhead loop)
*Single precision Floating Point Unit (IEEE-754 Compatible)
*Dedicated Integer divide unit
*18 data memory protection ranges, 10 code memory protection ranges arranged in 6 sets

=== Superscalar Architecture ===
The processor core within the AURIX™ TC3xx family, specifically the TC1.6.2P implementation, employs a superscalar architecture characterized by three parallel pipelines: the Integer Pipeline, the Load/Store Pipeline, and the Loop Pipeline. Superscalar execution is a form of instruction-level parallelism that enables the processor to issue and execute multiple instructions during a single clock cycle. The TriCore™ TC3xx core's superscalar architecture allows it to issue and execute multiple instructions in parallel. Specifically, it can issue up to two instructions simultaneously to the Integer and Load/Store pipelines. However, there are certain constraints on this dual issuing capability. For example, back-to-back data arithmetic instructions can only be issued in separate cycles, and a load/store instruction can be issued either on its own or paired with a data arithmetic instruction, provided the load/store instruction is the second in the pair. Under ideal conditions, with careful instruction scheduling, this dual-issue capability can lead to a throughput of close to 0.5 clock cycles per instruction, effectively executing two instructions per cycle.

=== Pipeline Stages ===
The execution of instructions within the TriCore™ TC3xx core is managed through a pipeline consisting of several stages. In one document it is mentioned that the pipeline consists of 6 stages <ref name="ref3635926" />, but the exact stages remain unclear. From the architecture the following stages can be inferred:

* '''Fetch Stage''': The initial stage in the pipeline is the Fetch stage, where instructions are retrieved from memory. This task is handled by the Instruction Fetch Unit (IFU), which is responsible for fetching instructions from the memory system. To improve efficiency, the IFU employs a pre-fetching mechanism, anticipating the instructions that will be needed and bringing them into the processor before they are actually required. Instructions are fetched through a 64-bit wide Program Memory Interface (PMI), allowing for the retrieval of a significant amount of instruction data in each cycle. The fetched instructions are then placed into an issue FIFO, a buffer capable of holding up to six instructions. This buffer plays a crucial role in managing the flow of instructions to the subsequent execution pipelines. The 64-bit fetch width and the instruction buffer are indicative of a design that aims to ensure a continuous supply of instructions to the pipelines, preventing them from being starved of work. A wider fetch path allows for more instruction bits to be obtained from memory in each clock cycle, while the buffer helps to mitigate temporary delays in instruction fetching.
* '''Execution Unit''': The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop Pipeline. All three pipelines operate in parallel and are capable of executing instructions simultaneously. Each pipline has its own decode stage and two execute stages. Furthermore, the TC3xx features a Floating Point Unit (FPU). It is not clear whether the FPU is part of the execution unit or a separate unit. It is assumed that the FPU also has its own decode stage and an unknown number of execute stages
** '''Decode Stage''': Following the Fetch stage, the instruction are issued to one of the pipelines. In the decode stage of each pipeline, the instruction is examined and translated to determine the specific operation it represents and to identify the operands it will operate on. It is assumed that operands are read from the register file during the decode stage.
** '''Execute Stage''': The Execute stage is where the actual operation specified by the instruction is carried out. Pipeline hazards (stalls) are minimised by the use of forwarding paths between pipeline stages allowing the results of one instruction to be used by a following instruction as soon as the result becomes available.
** '''Writeback Stage''': The final stage in the pipeline is the Writeback stage. In this stage, the results produced by the executed instruction are written back to the processor's register file, making them available for subsequent instructions. It is unclear whether the writeback stage is part of the (two) execution stages or a separate stage.

=== Execution Pipelines ===
The TriCore™ TC3xx core leverages four parallel pipelines to enhance its performance. Each pipeline is designed to handle a specific class of instructions:

* '''Integer Pipeline:''' This pipeline is responsible for executing integer arithmetic and logical instructions, including data-conditional jump instructions, bit manipulation operations, as well as division and multiply-accumulate (MAC) instructions.
* '''Load/Store Pipeline:''' The primary function of this pipeline is to manage memory access operations, including loading data from memory and storing data to memory. It also handles address arithmetic, unconditional jump instructions, procedure call instructions, context-switching operations, and control flow related to context save areas (CSAs).
* '''Loop Pipeline:''' This is a specialized pipeline designed to facilitate zero-overhead loops, a technique that significantly improves the performance of iterative code sections. Its design aims to eliminate or minimize the overhead typically associated with loop control, such as incrementing counters and checking loop conditions. Some documentation suggests that the loop pipeline comes along with a "Loop Cache". This dedicated cache would likely be used to store instructions belonging to the loop, enabling very fast access and execution for repeated iterations.
* '''Floating Point Unit (FPU):''' The FPU is responsible for executing floating-point arithmetic operations

=== Store Buffers ===
The TriCore™ TC3xx core include '''Store Buffers''' to decouple memory write operations from CPU instruction execution. All stores from the Load/Store Pipeline are placed in the store buffer prior to being written to local memory or transferred via the bus system. Write data is taken from the store buffers and written to memory when the target memory or bus interface becomes available. In normal operation the CPU will prioritise memory load operations over store operations in order to improve performance unless the store buffer is full or the order of load and store operations must be preserved (e.g. peripheral space access). The store buffer can hold the data for up to 6 stores operations. To improve performance the store buffer will merge consecutive byte, half-word, and word writes of the same location to reduce the number of memory accesses required.

=== Instruction Timing ===

==Functional Safety and Security Features==
===Hardware Security Module and Encryption===
One of the defining features of the AURIX™ TC3xx family is its robust hardware-based security subsystem, implemented to protect against cyber threats and unauthorized manipulation of vehicle systems. Each TC3xx MCU includes a dedicated ''Hardware Security Module'' (HSM), which is essentially an on-chip co-processor with its own CPU and cryptographic engine designed to handle secure operations. In the second-generation AURIX™ (TC3xx), the HSM was upgraded with support for asymmetric cryptography (e.g., RSA, ECC algorithms) in hardware, providing significantly faster public-key encryption and authentication capabilities than pure software implementations. This HSM supports '''EVITA Full''' (the highest level of the EU’s EVITA automotive security requirements), meaning it can perform secure boot, message authentication, and encryption at a level suitable for protecting critical in-vehicle communications. For example, the HSM can encrypt and authenticate CAN/Ethernet messages to prevent spoofing or tampering on the vehicle network, and it can manage cryptographic keys securely isolated from the main application cores.<ref name="ref14281090104">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref2022357806" />

The security module enables features like '''secure boot''', where the AURIX™ will only execute firmware that is digitally signed by the vehicle manufacturer, thereby preventing unauthorized or malicious code. It also facilitates ''over-the-air (OTA) updates'' in a secure manner: the TC3xx HSM can verify and decrypt update packages received via telematics, allowing firmware upgrades while protecting against attackers attempting to hijack the software. In addition, the HSM includes a true random number generator and supports protocols for immobilizer and theft protection systems. Infineon’s implementation essentially treats the HSM as an “embedded smart card” inside the microcontroller. This approach, building on Infineon’s expertise in chip card security, helps to safeguard sensitive assets like cryptographic keys and to perform secure operations (encryption, decryption, authentication) in hardware, making attacks significantly more difficult. The strong cybersecurity provisions of the AURIX™ TC3xx have made it a preferred choice for vehicle gateway ECUs and central body controllers, which are points of entry for connected car communications and thus high-value targets for hackers. By incorporating the HSM, automotive OEMs can implement advanced security features such as encrypted onboard communication (to thwart bus tampering) and secure diagnostics, ensuring the vehicle’s electronic data is protected against cyber threats even as cars become more connected.<ref name="ref14281090104" /><ref name="ref5727814513">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref><ref name="ref19484776953">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
=== Functional Safety and Fault Tolerance===
Beyond cybersecurity, the AURIX™ TC3xx architecture is built with extensive ''functional safety'' features to meet the highest safety integrity levels in automotive systems. The multi-core design supports ''lockstep operation'', where redundant checker cores run in parallel with main cores and continuously compare results cycle-by-cycle. In TC3xx devices, up to four of the six TriCore™ CPUs have such lockstep partner cores, allowing the microcontroller to detect any single-point CPU failure instantly (if a discrepancy arises between the core and its checker, a fault is signaled). A ''Safety Management Unit (SMU)'' is integrated on-chip to monitor various fault conditions throughout the device – it aggregates error signals from the lockstep cores, memory ECC monitors, clock/watchdog monitors, and peripheral self-tests, and can initiate safe-state actions (like resetting the chip or signaling an error pin to an external supervisor) if a critical fault is detected. The AURIX™ safety concept also includes a distributed Memory Protection Unit (MPU) arrangement, with multiple memory protection contexts that prevent errant or malicious code from writing to wrong memory areas. This helps contain faults and eases the integration of software with mixed criticality (Infineon allows partitioning software components of different ASIL levels on the same MCU while keeping them isolated).<ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref19519075552">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref>

Crucially, the TC3xx family was developed according to ISO 26262 processes and can achieve '''ASIL-D''' (Automotive Safety Integrity Level D), the highest grade for automotive functional safety. Compared to a traditional dual-core lockstep approach, the AURIX’s™ multi-core safety architecture allowed Infineon to reduce certain safety development overheads (earlier Infineon data suggested up to 30% reduction in safety software workload) by providing built-in safety mechanisms and diagnostics. Infineon supplies a comprehensive safety manual and diagnostic libraries for the AURIX™, helping engineers utilize features like CPU self-tests, RAM tests, and CRC checks to comply with safety standards. In addition to automotive standards, the AURIX™ TC3xx has also been qualified for '''industrial safety''': in 2023, Infineon announced support for IEC 61508 metrics, enabling designs with AURIX™ to reach SIL-2 and SIL-3 safety integrity levels for industrial applications. This cross-industry safety compliance is facilitated by the MCU’s redundant design and detailed failure mode documentation (FMEDA) provided by Infineon. In summary, the AURIX™ TC3xx integrates both proactive safety (fault prevention via lockstep, monitoring and protection) and reactive safety (fault detection and safe shutdown), making it a dependable component for systems that cannot afford unintended behavior, whether in cars, factories, or aerospace. <ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref4967712052">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref><ref name="ref196858272">MCUs support industrial functional safety - Electronic Products https://www.electronicproducts.com/mcus-support-industrial-functional-safety/</ref>
== Platform Devices ==
The following table shows a feature overview of the AURIX™ TC3xx Platform family focusing on memory and number of cores.
{| class="wikitable"
!
!Feature
!TC33x
!TC33xEXT
!TC35x
!TC36x
!TC37x
!TC37xEXT
!TC38x
!TC39x
|-
| rowspan="2" |CPUs
|Cores / Checker Cores
|1 / 1
|2 / 1
|3 / 2
|2 / 2
|3 / 2
|3 / 3
|4 / 2
|6 / 4
|-
|Max. Freq.
| colspan="8" |300 MHz
|-
| rowspan="2" |Cache per CPU
|Program [KB]
| colspan="8" |32
|-
|Data [KB]
| colspan="8" |16
|-
| rowspan="3" |SRAM per CPU
|PSPR [KB]
|8
|{{rev|32|CPU0}}
{{rev|64|other}}
|64
|32
|64
|64
|64
|64
|-
|DSPR [KB]
|192
|{{rev|192|CPU0}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|192
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|-
|DLMU [KB]
|8
|{{rev|8|CPU0}}
{{rev|64|other}}
|64
|64
|64
|64
|64
|64
|-
| rowspan="2" |SRAM global
|LMU [KB]
| -
| -
|512
| -
| -
| -
|128
|768
|-
|DAM [KB]
| -
| -
|32
| -
|64
|64
|128
|128
|-
| rowspan="3" |Extension Memory (EMEM)
|TCM [MB]
| -
|1
|2
| -
| -
|2
| -
|2
|-
|XCM [MB]
| -
| -
| -
| -
| -
|1
| -
|2
|-
|XTM [KB]
| -
|16
|16
| -
| -
|16
| -
|16
|-
| rowspan="2" |Program Flash
|Size [MB]
|2
|4
|4
|4
|6
|10
|10
|16
|-
|Banks [MB]
|1 x 2
|2 x 2
|2 x 2
|2 x 2
|2 x 3
|3 x 3, 1 x 1
|3 x 3, 1 x 1
|5 x 3, 1 x 1
|-
| rowspan="2" |Data Flash
|DF0 Size (single-ended) [KB]
|128
|128
|128
|128
|256
|512
|512
|1024
|-
|DF1 Size (single-ended) [KB]
|128
|128
|128
|128
|128
|128
|128
|128
|-
| rowspan="3" |DMA
|Channels
|64
|64
|64
|64
|128
|128
|128
|128
|-
|Move Engines
|2
|2
|2
|2
|2
|2
|2
|2
|-
|Resource Partitions
|4
|4
|4
|4
|4
|4
|4
|4
|}

== Compilers ==
The AURIX™ TC3xx family is a series of high-performance microcontrollers widely used in automotive and industrial applications. Compilers for the AURIX™ TC3xx are crucial for developers aiming to optimize performance, reliability, and safety in their applications. One significant aspect of the compiler landscape for AURIX™ TC3xx is the limited direct support from mainline open-source compilers such as GCC or LLVM/Clang. The primary reason for this is the stringent requirements for functional safety in automotive and industrial applications, which demand specialized features and compliance with safety standards that are often not met by general-purpose open-source compilers.

=== Commercial Compilers ===

# '''Tasking''': Tasking compilers are renowned for their robust support for automotive applications, offering advanced debugging capabilities and optimization techniques tailored for the AURIX™ architecture. They provide extensive code optimization, comprehensive debugging tools, and strong support for safety standards such as ISO 26262, making them ideal for developing high-performance, reliable, and safe applications.
# '''HighTec''': The HighTec compiler is a popular choice, known for its Eclipse-based development environment and strong multicore support. HighTec provides both GCC and LLVM-based ports of open-source compilers tailored specifically for the AURIX™ TC3xx family. These compilers offer efficient parallel execution, advanced code analysis, and an integrated development environment, ensuring robust performance and compliance with safety standards.
# '''Green Hills Software''': Green Hills Software provides a highly optimized toolchain aimed at safety-critical applications, focusing on high performance and strict compliance with automotive standards. Their compiler offers superior optimization, extensive safety features, and a proprietary IDE with specialized tools for automotive development, ensuring developers can meet the stringent demands of functional safety.

=== GCC for AURIX™ ===

While mainline GCC does not directly support the AURIX™ TC3xx family, there is an unofficial GCC version available for AURIX™. Due to the GNU General Public License (GPL), the source code from HighTec was retrieved and, along with binary versions, published on GitHub:

*GCC 4.9.4/Binutils 2.20/Newlib 1.18 for Tricore™ AURIX™ [[https://github.com/volumit/package_494 Source]] [[https://github.com/volumit/tricore_gcc494_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc494_linux_bins Prebuild Linux Binaries]]
*GCC 9.4.0/Binutils 2.20/Newlib 1.18 for Tricore™ AURIX™ [[https://github.com/volumit/package_940 Source]] [[https://github.com/volumit/tricore_gcc940_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc940_linux_bins Prebuild Linux Binaries]]
*GDB 10.0.50 for Tricore™ AURIX™ [[https://github.com/volumit/gdb-tricore Source]]
==emmtrix Tools for AURIX™ TC3xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX™ TC3xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

==See Also==

*[[Infineon AURIX TC4x|Infineon AURIX™ TC4x]]
*[[Infineon AURIX TC2xx|Infineon AURIX™ TC2xx]]
*[[TriCore Instruction Set Architecture]]

==External Links==

*https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/
*[https://documentation.infineon.com/aurixtc3xx/docs/qmd1702366622648 AURIX™ TC3xx user manuals]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d3605221d96 AURIX™ TC3xx User Manual Part-1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d35f8541d94 AURIX™ TC3xx User Manual Part-2]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd AURIX™ TC3xx Architecture vol 1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 AURIX™ TC3xx Architecture vol 2]

== References ==
<references />
[[Category:Supported Architectures]]

{{#seo:
|title=Infineon AURIX TC3xx Family – Deep Dive
|description=This deep dive into Infineon's AURIX TC3xx family explores its multi-core TriCore architecture, real-time capabilities, safety and security features and tools
|image=File:AURIX_TC399_LFBGA-516_plain.jpg
|keywords=AURIX, Infineon, TC3xx, microcontroller, TriCore, automotive, ADAS, ISO 26262, functional safety, embedded security, ASIL-D, deep dive
}}

Infineon AURIX TC2xx

2025-04-08T08:34:51Z

Mira.steinmetz:

'''Infineon AURIX™ TC2xx''' is a family of 32-bit automotive microcontrollers developed by Infineon Technologies. ''AURIX™'' stands for ''“Automotive Realtime Integrated Next Generation Architecture”'', reflecting its design for real-time, safety-critical automotive applications<ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. The TC2xx series (first-generation AURIX™) is based on a multicore architecture featuring up to three independent 32-bit '''TriCore™''' processor cores. Introduced around 2012, the AURIX™ TC2xx marked Infineon’s transition to a multicore microcontroller platform (fabricated in 65 nm technology) after earlier single-core TriCore™ generations. It was designed from the ground up to meet stringent automotive safety requirements (ISO 26262) and to provide higher performance and integration for applications like engine management, chassis control, and driver assistance systems.<ref name="ref1222155140" /><ref name="ref1490396573">Optimized for Success - EE Times Europe https://www.eetimes.eu/optimized-for-success/</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>

The AURIX™ TC2xx family’s design philosophy is to combine '''safety''', '''security''', and '''performance''' in one scalable MCU platform. It achieves high functional safety compliance (up to '''ASIL-D''', the highest automotive safety integrity level) with less development effort compared to traditional dual-controller lockstep systems<ref name="ref572781451" />. Infineon claims that using AURIX™ can cut safety-related development time by ~30% versus classical lockstep architectures, thanks to its built-in fault detection and monitoring hardware. At the same time, the TC2xx provides significant performance headroom – roughly 50% to 100% higher computational performance compared to its predecessors – while maintaining power consumption similar to previous single-core designs. To address emerging automotive security needs, the AURIX™ MCUs also integrate a dedicated Hardware Security Module ('''HSM''') on-chip, which protects against IP theft, fraud, and tampering. This combination of features makes the AURIX™ TC2xx a popular choice for consolidating various automotive control functions (powertrain, safety, body, etc.) onto one platform, without sacrificing reliability or efficiency.<ref name="ref572781451" /><ref name="ref71179009">32-bit TriCore™ AURIX™– TC2xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/</ref>
==Architecture==
The AURIX™ TC2xx is built on Infineon’s '''TriCore™''' architecture, which uniquely unifies traits of a RISC processor, a microcontroller, and a DSP (digital signal processor) into one core design. Each TriCore™ CPU in the TC2xx is a 32-bit superscalar processor that supports both 32-bit and 16-bit instruction formats (the latter for code size efficiency). The TriCore™ instruction set architecture includes typical RISC features (load/store architecture, 4 GB address space) and DSP capabilities (such as multiply-accumulate instructions and bit manipulation) in a single core. The cores also have an optional floating-point unit (FPU) and support SIMD (single-instruction multiple-data) operations for signal processing acceleration. The maximum core frequency in the TC2xx family is 300 MHz, and devices achieve about 1.7–2.4 DMIPS/MHz per core, providing robust real-time performance.<ref name="ref1222155140" /><ref name="ref71179009" />

In terms of core configuration, high-end AURIX™ TC2xx models implement three main TriCore™ CPUs, which can be run in parallel or in redundant (lockstep) pairs for safety. Some variants include a redundant checker core that shadows a primary core to detect calculation errors (a technique to meet SIL/ASIL safety goals). The multicore architecture is supported by a layered memory system: each TriCore™ has tightly coupled local memory for fast instruction and data access, and they share access to large on-chip Flash and RAM via an internal bus matrix. Memory options in the TC2xx range from about '''0.5 MB up to 8 MB of on-chip Flash''', and from ~50 KB up to 2.7 MB of SRAM, depending on the specific device. This on-chip memory (with ECC protection on memories for safety) allows real-time code execution and data storage without external memory in most use cases. For peripherals and I/O, the AURIX™ architecture includes a rich set of on-chip modules connected via internal buses, such as analog-to-digital converters, timer units, communication interfaces, and direct memory access (DMA) controllers. AURIX™ TC2xx MCUs typically provide interfaces like multiple CAN/CAN-FD channels, LIN/UART, SPI, I²C, Ethernet (on higher-end models), and automotive-specific buses (e.g. FlexRay on some variants), making the chip a self-contained controller for complex automotive networks.'''<ref name="ref572781451" />'''<ref name="ref71179009" /><ref name="ref957370148">Infineon TriCore - Wikipedia https://en.wikipedia.org/wiki/Infineon_TriCore</ref>

The '''Generic Timer Module (GTM)''' is a notable part of the AURIX™ TC2xx architecture. It is a sophisticated timer/co-processor integrated on-chip to handle complex timing, PWM generation, input capture, and other signal conditioning tasks across more than 200 channels. There are also specialized accelerators and co-processors on certain TC2xx devices, such as a '''Hardware Fast Fourier Transform (HFFT)''' unit for signal processing and a '''Parallel Pixel Processor''' for simple video or sensor data processing. These dedicated engines offload the TriCore™ CPUs for specific high-load tasks (e.g. radar signal FFTs or encoder signal processing), improving overall throughput in automotive applications. The AURIX™ architecture uses a single-power supply (5V or 3.3V) design and includes an on-chip voltage regulator (EVR), simplifying power management. The MCUs are offered in a variety of package types (from compact QFP-64 up to large BGA-516) to accommodate different I/O needs. Overall, the TC2xx architecture is highly integrated and optimized for real-time, combining multiple CPU cores with ample flash memory, SRAM, and peripherals on one chip to serve as a '''central control unit''' in vehicles.<ref name="ref1222155140" /><ref>AURIX™ Unleashed - RS Components https://docs.rs-online.com/0f3f/0900766b815c315c.pdf</ref>
====CPU access latency (TC29x) ====
{| class="wikitable"
!CPU Access Type!!Local CPU
|-
|Data read access to own DSPR||0
|-
|Data write access to own DSPR||0
|-
|Data read access to own or other PSPR||8
|-
|Data write access to own or other PSPR||0
|-
|Data read access to other DSPR||8
|-
|Data write access to other DSPR||0
|-
|Instruction fetch from own PSPR
|0
|-
|Instruction fetch from other PSPR (critical word)||8
|-
|Instruction fetch from other PSPR (any remaining words)||0
|-
|Instruction fetch from other DSPR (critical word)||8
|-
|Instruction fetch from other DSPR (any remaining words)||0
|-
|Initial Pflash Access (critical word)||7 + configured PFlash Wait States
|-
|Initial Pflash Access (remaining words)||0
|-
|PMU PFlash Buffer Hit (critical word)||6
|-
|PMU PFlash Buffer Hit (remaining words)||0
|-
|Initial Dflash Access||7 + configured DFlash Wait States
|-
|TC1.6P Data read from System Peripheral Bus (SPB)
|{{rev|4|2=fCPU = fSPB}} {{rev|7|2=fCPU = 2*fSPB}} {{rev|10|2=fCPU = 3*fSPB}}
|-
|TC1.6P Data write to System Peripheral Bus (SPB)||0
|}
*

==Key Features==

* '''Safety Mechanisms:''' The AURIX™ TC2xx was developed via an ISO 26262-compliant process and includes multiple hardware mechanisms to achieve '''functional safety up to ASIL-D'''. Notably, it supports ''lockstep'' operation, where one or two of the TriCore™ CPUs can run in redundant lockstep mode with another core to detect discrepancies (faults) cycle-by-cycle. A Safety Management Unit ('''SMU''') is built in to monitor critical system parameters and handle faults. The architecture employs memory protection units and safe internal communication buses to isolate and supervise different software domains. Other safety features include '''error-correcting code (ECC)''' on flash and RAM, redundant peripherals (for example, duplicated ADC channels), watchdog timers, clock and voltage monitors, and self-test routines. These features allow developers to more easily implement safety-critical functions and meet standards like IEC 61508 (SIL-3) or ISO 26262 (ASIL-D) using a single AURIX™ MCU, whereas achieving the same on a traditional single-core MCU might require additional external safety ICs or companion processors.<ref name="ref1490396573" /><ref name="ref572781451" />
* '''Security Functions:''' Infineon integrated a dedicated Hardware Security Module ('''HSM''') into the AURIX™ TC2xx family to address automotive cybersecurity requirements. This HSM is essentially an on-chip co-processor (with its own CPU and flash) that handles cryptographic operations and secure key storage isolated from the main cores. It follows the EVITA (E-safety Vehicle Intrusion Protected Applications) guidelines for automotive security. The HSM enables features like secure boot, encryption/decryption, authentication, and detection of software tampering. By having a built-in “embedded smart card” for security, the AURIX™ can implement anti-theft, anti-cloning, and secure onboard communication measures without needing an external security chip. This integration is a key differentiator, as it helps protect vehicle functions (e.g. immobilizers, firmware updates, V2X communication) against hacking and unauthorized modifications.<ref name="ref1222155140" /><ref name="ref71179009" />
* '''Performance and DSP Capability:''' Each TriCore™ CPU in the TC2xx is capable of up to 300 MHz operation, and combined the multicore setup offers considerable processing power for an MCU (Infineon cites up to ~1.8 GFLOPS of DSP throughput for the highest models). The TriCore™ design delivers around '''1.7–2.4 DMIPS/MHz''' per core, meaning a triple-core AURIX™ at max frequency can exceed 2000 DMIPS of total throughput. The inclusion of DSP instructions and dedicated accelerators enables the AURIX™ to handle computationally intensive tasks (like control algorithms, filtering operations, or even rudimentary neural networks) that previously might require a separate DSP or FPGA. A built-in '''Floating Point Unit''' on each core supports single-precision (and optional double-precision in some cases) arithmetic, beneficial for model-based control algorithms and automotive sensor processing. Peripherals like the '''Generic Timer Module (GTM)''' and '''Hardware FFT''' accelerator (available on select TC2xx variants) further boost real-time performance for handling high-frequency events (e.g. engine ignition timing, motor control PWM, radar signal analysis) without overloading the CPU. Despite the performance, the TC2xx was designed with efficiency in mind; Infineon managed to double the performance over the prior generation (TC1xx AUDO) while keeping power consumption at comparable levels. The MCUs also support various low-power modes and a standby controller to minimize energy usage when parts of the system are idle.<ref name="ref1222155140" /><ref name="ref572781451" />
* '''Power and Integration:''' As a system-on-chip for vehicles, AURIX™ TC2xx integrates a wide range of '''communication interfaces''' and analog/digital peripherals. Common features include multiple CAN bus controllers (often with CAN FD support), LIN/UART, SPI and I²C channels, FlexRay communication in high-end models, and even Ethernet (in variants aimed at gateway or ADAS roles). High-resolution '''ADC units''' (with shared and redundant channels) allow precise sensor measurements for engine or chassis control. There are also specialized modules like delta-sigma ADCs and SENT interfaces for automotive sensor inputs. This rich peripheral set reduces the need for external components, helping to lower the overall system Bill of Materials. The TC2xx devices operate over a broad temperature range (typically –40 °C to +150 °C), meeting the demands of under-the-hood automotive environments. They run from a single supply (with internal regulators), simplifying designs, and support both 5 V and 3.3 V systems for compatibility with a variety of sensors and actuators. Combined with its safety and security features, the AURIX’s™ high integration makes it a one-chip solution for many complex embedded applications.<ref name="ref1222155140" /><ref name="ref1490396573" /><ref name="ref71179009" /><ref name="ref957370148" />

==Applications==
The Infineon AURIX™ TC2xx family is primarily targeted at the '''automotive industry''', especially domains requiring high reliability and real-time control. Its initial use cases were in '''powertrain''' and engine management systems – for example, controlling combustion engines, managing fuel injection and ignition, and coordinating electric motor and battery systems in hybrid or electric vehicles. The multi-core AURIX™ can run multiple control algorithms in parallel (e.g. for an engine’s cylinders, transmission and motor inverter concurrently), which is valuable in modern electrified powertrains. Beyond engines, AURIX™ TC2xx MCUs are used in '''chassis and safety systems''': they can serve as the central controller for '''anti-lock braking systems (ABS)''' and stability control, '''airbag control units''', '''electric power steering (EPS)''' systems, and suspension controllers. Advanced Driver Assistance Systems ('''ADAS''') and autonomous driving modules in earlier generations of vehicles have also employed AURIX™ for tasks such as sensor fusion, radar signal processing, and acting as a safety supervisor for driving assistance features<ref name="ref572781451" />. For example, a radar unit for adaptive cruise control might use an AURIX™ to perform real-time signal processing (using its DSP capabilities and HFFT) and make high-level decisions, all within an ASIL-D safe environment.<ref name="ref572781451" /><ref name="ref1228701036">https://resources.tasking.com/sites/default/files/2021-02/Take%20Advantage%20of%20Infineon%20AURIX%20TC3xx%20Family%20With%20the%20Right%20Compiler_WEB.pdf</ref>

Thanks to its safety certification and robust design, the AURIX™ TC2xx has seen adoption in any application that cannot tolerate failure. This includes '''industrial automation and robotics''', where the MCU’s reliability and support for functional safety (IEC 61508) are attractive. In industrial motor drives or robotics controllers, an AURIX™ might handle precise motor control algorithms and system monitoring. Other use cases outside pure automotive include '''commercial vehicles and transportation''' (trucks, agricultural and construction machinery), which have similar safety and durability requirements. The AURIX’s™ extensive communication interfaces also make it suitable as a gateway or central node in complex networks – for instance, acting as a domain controller in modern automotive E/E architectures to coordinate data between powertrain, body, and ADAS subsystems. Some '''electric vehicle (EV)''' platforms use AURIX™ MCUs in battery management systems and inverter controls, leveraging its calculation power for battery algorithms and its safety for monitoring cell health. In summary, the TC2xx family finds use in scenarios that demand '''real-time performance with high safety integrity''', predominantly in automotive (engine, transmission, chassis, safety, ADAS) but also in high-end industrial embedded systems.<ref name="ref71179009" /><ref name="ref1228701036" />

==emmtrix Tools for AURIX™ TC2xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX™ TC2xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ TC2xx / [[Infineon AURIX TC3xx|TC3xx]]/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

== See Also ==

* [[Infineon AURIX TC3xx|Infineon AURIX™ TC3xx]]
* [[Infineon AURIX TC4x|Infineon AURIX™ TC4x]]
* [[TriCore Instruction Set Architecture|TriCore™ Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/
* [https://www.infineon.com/dgdl/Infineon-TC29x_B-step-UM-v01_03-EN.pdf?fileId=5546d46269bda8df0169ca1bdee424a2 TC29x B-Step User Manual]

== References ==
<references />
[[Category:Supported Architectures]]

TriCore Instruction Set Architecture

2025-04-08T08:31:37Z

Mira.steinmetz:

TriCore™ is a unified, 32-bit microcontroller-DSP, single-core architecture optimized for real-time embedded systems. The ISA supports a uniform, 32-bit address space, with optional virtual addressing and memory-mapped I/O. The architecture allows for a wide range of implementations, ranging from scalar through to superscalar, and is capable of interacting with different system architectures, including multiprocessing. This flexibility at the implementation and system levels allows for different trade-offs between performance and cost at any point in time.

The architecture supports both 16-bit and 32-bit instruction formats. All instructions have a 32-bit format. The 16-bit instructions are a subset of the 32-bit instructions, chosen because of their frequency of use. These instructions significantly reduce code space, lowering memory requirements, system and power consumption.

Real-time responsiveness is largely determined by interrupt latency and context-switch time. The high-performance architecture minimizes interrupt latency by avoiding long multi-cycle instructions and by providing a flexible hardware-supported interrupt scheme. The architecture also supports fast-context switching.

== History ==
[[File:Tricore History.png|center|thumb|726x726px|Evolution of TriCore families<ref name=":0">Welcome to the next generation AURIX™ TC4x, Thomas Boehm, Senior Vice President Automotive Microcontroller, 12 January 2022, https://www.infineon.com/dgdl/Infineon_AURIX_TC4x.pdf?fileId=8ac78c8b7e4b5364017e4e1a407c0001</ref>]]Infineon’s TriCore™ architecture, which underpins the AURIX™ family, has a lineage dating back to the late 1990s. The first TriCore™-based microcontrollers were introduced in 1999 as the Infineon '''AUDO''' family (Automotive unified processor), marking the debut of a 32-bit core unifying RISC, microcontroller, and DSP capabilities. Over the next decade, Infineon released several generations of TriCore™-based AUDO MCUs (with increasing performance and integration), establishing a strong presence in automotive powertrain control units. The major breakthrough came in 2012 when Infineon announced the '''AURIX™''' family (the name AURIX™ being an acronym reflecting its automotive real-time focus) as the next evolution of TriCore™ micros. The first-generation AURIX™ (commonly referred to as [[Infineon AURIX TC2xx|AURIX TC2xx]]) featured up to three 32-bit TriCore™ CPUs at 200–300 MHz, with two of the cores optionally arranged in a lockstep pair for safety. These devices, manufactured on a 65 nm process, offered up to about 4–8 MB of flash memory and were among the first automotive MCUs to include a hardware security module for encryption. The AURIX™ TC2xx family quickly became a '''benchmark''' for automotive microcontrollers, combining high real-time performance with built-in safety and security, and saw adoption in various vehicle domains from engine management to chassis and ADAS.<ref name="ref507313680">History of TriCore™ - Infineon Technologies https://www.infineon.com/cms/en/product/promopages/historyoftricore/</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref><ref name="ref1951907555">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref>

As of January 2022, Infineon has shipped over '''845 million''' TriCore™ devices, including more than '''320 million''' AURIX™ microcontrollers. TriCore™ has proven to be the '''trusted choice for the automotive industry''', with total shipments expected to surpass '''1 billion units''' by the end of 2022. The '''success story began in the powertrain domain''' and subsequently expanded to cover the entire automotive MCU market.<ref>Welcome to the next generation AURIX™ TC4x, Thomas Boehm, Senior Vice President Automotive Microcontroller, 12 January 2022</ref>

The '''[[Infineon AURIX TC3xx|AURIX TC3xx]]''' (second-generation AURIX™) was announced in October 2016 as a major upgrade over the first generation, targeting the emerging needs of automated and electric vehicles. While maintaining software and pin compatibility with the TC2xx family, the TC3xx generation doubled the number of cores (scaling up to six TriCore™ cores) and moved to a smaller geometry 40 nm process to integrate larger memories and new peripherals. Key improvements introduced with TC3xx included: higher total processing performance (achieving 3× the real-time computing capability of its predecessor), increased on-chip flash (up to 16 MB) and SRAM (>6 MB) to accommodate the growing software in vehicles, a enhanced HSM with full EVITA support for cybersecurity, and new connectivity options like Gigabit Ethernet and more CAN FD channels to handle the data fusion requirements of ADAS. The TC3xx also introduced dedicated radar processing units (SPUs) to support level 2+ and level 3 autonomous driving systems that process radar sensor data on the MCU. Engineering samples of the flagship 300 MHz, 6-core TC39x became available in 2017, and the family entered volume production by 2019 once it achieved full automotive qualification. The seamless backward compatibility eased the migration for automakers and Tier-1 suppliers, allowing them to leverage existing AURIX™ TC2xx software and safety concepts on the more powerful TC3xx platform.<ref name="ref1428109010">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref1948477695">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref><ref name="ref2022357806">UDE Debug, Trace and Test solutions for Infineon TriCore™ AURIX™ TC32, TC33, TC35, TC36, TC37, TC38, TC39, TC3x Microcontrollers https://www.pls-mc.com/products/infineon-tricore-aurix-tc32-tc33-tc35-tc36-tc37-tc38-tc39-microcontrollers/</ref>

As of the mid-2020s, Infineon has continued to evolve the AURIX™ lineage. In 2023, the company revealed the third-generation '''[[Infineon AURIX TC4x|AURIX TC4x]]''' family, representing the 7th generation of TriCore™-based MCUs overall. The TC4x family (in development) is slated to bring further enhancements such as higher CPU frequencies, larger local memories, an enhanced TriCore™ core design with improved floating-point and virtualization support, and even the integration of auxiliary cores (including potentially heterogeneous cores). Notably, Infineon is also embracing emerging technology by planning to incorporate '''RISC-V''' processor cores alongside TriCore™ in future AURIX™ products, combining the proven safety of TriCore™ with the flexibility of the open RISC-V ecosystem. Throughout its history, the AURIX™ architecture’s roadmap has been driven by the increasing computational demands and safety requirements of modern vehicles – from the early single-core engine controllers to today’s multi-core domain controllers for autonomous driving. Each generation has built upon the last, adding more performance, memory, and features while preserving the fundamental focus on real-time determinism, safety, and security that the TriCore™ architecture was originally created for. <ref name="ref507313680" /><ref name="ref1329056342">Infineon brings RISC-V to the automotive industry and is first to announce an automotive RISC-V microcontroller family – RISC-V International https://riscv.org/ecosystem-news/2025/03/infineon-brings-risc-v-to-the-automotive-industry-and-is-first-to-announce-an-automotive-risc-v-microcontroller-family/</ref>

As of January 2022, Infineon has shipped over '''845 million''' TriCore™ devices, including more than '''320 million''' AURIX™ microcontrollers. TriCore™ has proven to be the '''trusted choice for the automotive industry''', with total shipments expected to surpass '''1 billion units''' by the end of 2022. The '''success story began in the powertrain domain''' and subsequently expanded to cover the entire automotive MCU market.<ref name=":0" />
==Versions==
{| class="wikitable"
|+
!ISA
!Processors
!User Manual Date
!New Instructions
|-
|TC1.3
|
|2002-05
|
|-
|TC1.3.1
|[https://www.infineon.com/cms/en/product/microcontroller/legacy-microcontroller/other-legacy-mcus/audo-family/ TriCore™ Family AUDO MAX]
|2007-11
|
*CACHEI.W, CACHEI.WI

*FTOIZ, FTOQ31Z, FTOUZ (FPU Conversion Instructions)
|-
|TC1.6
|[[Infineon AURIX TC2xx]]
| 2013-07
|
*DISABLE, RESTORE, CACHEI.I (Interrupt and Data Cache manipulation)
*DIV, DIV.U (Fast Integer Divide)
*FCALL,FCALLA,FCALLI, FRET (fast call and return with minimal saving of state)
*LD.BU, LD.B, LD.HU, LD.H, ST.B, ST.H, ST.A (Long offset addressing mode introduced for byte, half word and address accesses)
*JEQ, JNE (Extended range of 16 bit jumps)
*CMPSWAP.W, SWAPMSK.W (New Synchronisation Instructions)
*CRC32 (New CRC instruction)
*WAIT (New wait for interrupt instruction)
|-
|TC1.6.2
|[[Infineon AURIX TC3xx]]
|2017-01
|
*CRC32B.W, CRC32L.W, CRC32.B (CRC32 for big endian, little endian and byte data)
*CRCN (arbitrary width and polynomial CRC calculation)
*SHUFFLE (Reorder bytes within word)
*POPCNT (count number of bits set in word)
* FTOHP, HPTOF (Half precision floating point conversion)
*LHA (Load high bits of address value)
|-
|TC1.8
|[[Infineon AURIX TC4x]]
| N/A
|N/A (user manual not yet public available)
|}

== Features==
The key features of the TriCore™ Instruction Set Architecture (ISA) are:

*32-bit load store architecture
*4 Gbyte address range (232)
*16-bit and 32-bit instructions for reduced code size
*Data types:
**Boolean, integer with saturation, bit array, signed fraction, character, double-word integers, signed integer, unsigned integer, IEEE-754 single-precision floating point

*Data formats:
**Bit, byte (8-bits), half-word (16-bits), word (32-bits), double-word (64-bits)
*Byte and bit addressing
*Little-endian byte ordering for data, memory and CPU registers
*Multiply and Accumulate (MAC) instructions: Dual 16 × 16, 16 × 32, 32 × 32
*Saturation integer arithmetic
*Packed data
*Addressing modes:
**Absolute, circular, bit reverse, long + short, base + offset with pre- and post-update
*Instruction types:
**Arithmetic, address arithmetic, comparison, address comparison, logical, MAC, shift, coprocessor, bit logical, branch, bit field, load/store, packed data, system

*General Purpose Register Set (GPRS):
**Sixteen 32-bit data registers
**Sixteen 32-bit address registers
**Three 32-bit status and program counter registers (PSW, PC, PCXI)
*Debug support (OCDS):
** Level 1, supported in conjunction with the CPS block
**Level 3, supported in conjunction with the MCDS block (Emulation Device only).
*Flexible memory protection system providing multiple protection sets with multiple protection ranges per set.

*Temporal protection system allowing time bounded real time operation

==Register Set==

===Architectural Registers===
The architectural registers consist of:

*32 General Purpose Registers (GPRs)
**16 Address Registers
**16 Data Registers
*Program Counter (PC)
*Two 32-bit registers containing status flags
{| style="margin: 1em 0"
|+32-bit Architectural Registers
| style="vertical-align:top" |
{| class="wikitable" style="margin: 0 1em"
|-
! colspan="2" |Address Register
|-
|A[15]
|Implicit Base Address
|-
|A[14]||
|-
| A[13]||
|-
|A[12]||
|-
|A[11]||Return Address
|-
|A[10]|| Stack Pointer (SP)
|-
|A[9]||Global Address Register
|-
|A[8]|| Global Address Register
|-
|A[7]||
|-
|A[6]||
|-
|A[5]||
|-
|A[4]||
|-
|A[3]||
|-
| A[2]||
|-
|A[1]
|Global Address Register
|-
| A[0]||Global Address Register
|}
| style="vertical-align:top" |
{| class="wikitable" style="margin: 0 1em"
|-
! colspan="2" | Data Register
|-
|D[15]||Implicit Data
|-
|D[14]||
|-
|D[13]||
|-
|D[12]||
|-
|D[11]||
|-
|D[10]||
|-
|D[9]||
|-
|D[8]||
|-
|D[7]||
|-
|D[6]||
|-
|D[5] ||
|-
|D[4]||
|-
|D[3]||
|-
|D[2]||
|-
|D[1]||
|-
|D[0]||
|}
| style="vertical-align:top" |
{| class="wikitable" style="margin: 0 1em"
|-
! colspan="2" |System Register
|-
|PCXI||Previous Context Information
|-
|PSW||Program Status Word
|-
|PC||Program Counter
|}
|}

===Special Registers===
{| class="wikitable"
! colspan="2" |General Special Registers
|-
| PC||Program Counter Register
|-
|SYSCON
|System Configuration Register
|-
|CPU_ID||CPU Identification Register (Read Only)
|-
|CORE_ID|| Core Identification Register
|-
|BIV||Base Address of Interrupt Vector Table Register
|-
|BTV||Base Address of Trap Vector Table Register
|-
|ISP||Interrupt Stack Pointer Register
|-
|ICR||ICU Interrupt Control Register
|-
|FCX||Free Context List Head Pointer Register
|-
|LCX||Free Context List Limit Pointer Register
|-
|COMPAT||Compatibility Mode Register
|}

{| class="wikitable"
! colspan="2" |Debug Registers
|-
|DBGSR
|Debug Status Register
|-
|EXEVT||External Event Register
|-
|CREVT||Core Register Event Register
|-
|SWEVT||Software Event Register
|-
| TR0EVT||Trigger Event 0 Register
|-
|TR0ADR||Trigger Address 0 Register
|-
|⋮||
|-
|TR7EVT
|Trigger Event 7 Register
|-
|TR7ADR||Trigger Address 7 Register
|-
|TRIG_ACC|| Trigger Accumulator Register
|-
|DMS||Debug Monitor Start Address Register
|-
|DCX||Debug Context Save Address Register
|-
|TASK_ASI||TASK Address Space Identifier Register
|-
|DBGTCR||Debug Trap Control Register
|-
|CCTRL
|Counter Control Register
|-
|CCNT||CPU Clock Count Register
|-
|ICNT||Instruction Count Register
|-
|M1CNT||Multi Count Register 1
|-
| M2CNT||Multi Count Register 2
|-
|M3CNT||Multi Count Register 3
|}

{| class="wikitable"
! colspan="2" |Floating Point Registers
|-
|FPU_TRAP_CON||Trap Control Register
|-
|FPU_TRAP_PC||Trapping Instruction Program Control Register
|-
|FPU_TRAP_OPC||Trapping Instruction Opcode Register
|-
|FPU_TRAP_SRC1||Trapping Instruction SRC1 Operand Register
|-
|FPU_TRAP_SRC2||Trapping Instruction SRC2 Operand Register
|-
|FPU_TRAP_SRC3||Trapping Instruction SRC3 Operand Register
|}

==Instructions Set==

===Pipeline===
{| class="wikitable"
|+
!Acronym
!Pipeline
|-
|LS
|Load/Store
|-
|IP
|Integer Pipeline
|-
|FPU
|Floating Point Unit
|}

===Classes===
{| class="wikitable"
!Class
!Pipeline
!Description
!Example
|-
|Arithmetic
|LS
|Arithmetic operations involving addresses.
|ADD.A, ADDIH.A
|-
|Arithmetic
|IP
|Arithmetic operations involving integers.
| ADD, SUB
|-
|Cache
|LS
|Cache management operations.
|CACHEA.W, CACHEA.WI
|-
|Compare
|IP
| Comparison operations.
|EQ, GE
|-
|Control Flow
|LS
|Control flow instructions for branching.
|J, JNE.A
|-
|Control Flow
| IP
| Control flow operations for branching.
|JEQ, JLT
|-
|Coprocessor 0
|IP
|Special operations using coprocessor 0.
|CRC32.B, IXMAX
|-
|Count
|IP
|Counting bits in registers.
|CLO, CLZ
|-
|CSA Control Flow
|LS
|Context Save Areas (CSA) control flow instructions
|CALL, BISR
|-
| Extract
|IP
| Bit field extraction and manipulation.
|DEXTR, INS.T
|-
|Floating Point
|FPU
|Floating-point instructions
|ADDF, SUBF
|-
|Integer Divide
|IP
|Integer division operations.
|DIV, DVSTEP
|-
|Load
|LS
|Load data from memory.
|LD.A, LDUCX
|-
|Logical
|IP
|Bitwise logical operations.
|AND, OR
|-
|Move
|LS
|Move data between registers.
|MOV.A, MOV.AA
|-
|Move
|IP
|Move operations with conditions.
|CMOV, MOV
|-
|Multiply
|IP
|Multiplication operations.
|MUL, MULS
|-
|Multiply Accumulate
|IP
| Multiply and accumulate operations.
|MADD, MSUB
|-
|Shift
|IP
|Bit shift operations.
|SH, SHA
|-
|Store
|LS
|Store data to memory.
|ST.A, ST.B
|-
|Sync
|LS
|Synchronization operations.
|DSYNC, ISYNC
|-
|Trap and Interrupt
|LS
|Interrupt and trap operations.
| DEBUG, TRAPV
|}

===Instruction List===

{| class="wikitable sortable"
!Pipeline
!Class
!Mnemonic
!Longname
!ISA Version
|-
|LS
|Arithmetic
|ADD.A
|Add Address
|
|-
|LS
|Arithmetic
|ADDIH.A
|Add Immediate High to Address
|
|-
|LS
|Arithmetic
|ADDSC.A
|Add Scaled Index to Address

|
|-
|LS
|Arithmetic
|ADDSC.AT
|Add Bit-Scaled Index to Address
|
|-
|LS
|CSA Control Flow
|BISR
|Begin Interrupt Service Routine
|
|-
|LS
|Cache
|CACHEA.I
|Cache Address, Invalidate
|
|-
|LS
|Cache
|CACHEA.W
|Cache Address, Writeback
|TC1.3.1
|-
|LS
|Cache
|CACHEA.WI
|Cache Address, Writeback and Invalidate
| TC1.3.1
|-
|LS
|Cache
|CACHEI.W
|Cache Index, Writeback
|
|-
| LS
|Cache
|CACHEI.I
|Cache Index, Invalidate
|TC1.6
|-
|LS
|Cache
|CACHEI.WI

|Cache Index, Writeback, Invalidate
|
|-
|LS
|CSA Control Flow
|CALL
|Call
|
|-
|LS
|CSA Control Flow
|CALLA
|Call Absolute
|
|-
|LS
|CSA Control Flow
|CALLI
|Call Indirect
|
|-
|LS
|Load
|CMPSWAP.W
|Compare and Swap
|TC1.6
|-
| LS
|Trap and Interrupt
|DEBUG
|Debug
|
|-
|LS
|Trap and Interrupt
|DISABLE
|Disable Interrupts
|TC1.6
|-
|LS
|Sync
|DSYNC
|Synchronize Data

|
|-
|LS
|Trap and Interrupt
|ENABLE
|Enable Interrupts
|
|-
|LS
|Arithmetic
|EQ.A
|Equal to Address
|
|-
| LS
|Arithmetic
|EQZ.A
|Equal Zero Address
|
|-
|LS
|CSA Control Flow
|FCALL
|Fast Call
|TC1.6
|-
|LS
| CSA Control Flow
|FCALLA
|Fast Call Absolute
|TC1.6
|-
|LS
|CSA Control Flow
|FCALLI
|Fast Call Indirect
|TC1.6
|-
|LS
|CSA Control Flow
|FRET
|Return from Fast Call
|TC1.6
|-
|LS
|Arithmetic
|GE.A
|Greater Than or Equal Address
|
|-
|LS
|Sync
|ISYNC
|Synchronize Instructions
|
|-
|LS
|Control Flow
|J
|Jump Unconditional
|
|-
|LS
|Control Flow
|JA
|Jump Unconditional Absolute
|
|-
|LS
|Control Flow
|JEQ.A
|Jump if Equal Address
|
|-
|LS
|Control Flow
|JI
|Jump Indirect
|
|-
|LS
|Control Flow
|JL
|Jump and Link
|
|-
|LS
|Control Flow
|JLA
|Jump and Link Absolute
|
|-
|LS
| Control Flow
| JLI
|Jump and Link Indirect
|
|-
|LS
|Control Flow
|JNE.A
|Jump if Not Equal Address
|
|-
|LS
|Control Flow
|JNZ.A
|Jump if Not Equal to Zero Address
|
|-
|LS
|Control Flow
|JZ.A
|Jump if Zero Address
|
|-
|LS
|Load
|LD.A
|Load Word to Address Register
|
|-
|LS
|Load
|LD.B
|Load Byte
|TC1.6*
|-
|LS
|Load
|LD.BU
|Load Byte Unsigned
|TC1.6*
|-
|LS
|Load
|LD.D
|Load Double-word
|
|-
|LS
|Load
|LD.DA
|Load Double-word to Address Register
|
|-
|LS
|Load
|LD.H
|Load Half-word
|TC1.6*
|-
|LS
|Load
|LD.HU
|Load Half-word Unsigned
|TC1.6*
|-
|LS
| Load
|LD.Q
|Load Half-word Signed Fraction
|
|-
|LS
|Load
|LD.W
|Load Word
|
|-
|LS
| Load
|LDLCX
|Load Lower Context
|
|-
|LS
|Store
|LDMST
|Load-Modify-Store
|
|-
|LS
|Load
|LDUCX
|Load Upper Context
|
|-
|LS
|Load
|LEA
|Load Effective Address
|
|-
|LS
|Load
|LHA
|Load High Address
|TC1.6.2
|-
|LS
|Control Flow
|LOOP
|Loop
|
|-
|LS
|Control Flow
|LOOPU
|Loop Unconditional
|
|-
|LS
|Arithmetic
|LT.A
|Less Than Address
|
|-
|LS
|Move
|MFCR
|Move From Core Register

|
|-
|LS
|Move
|MOV.A
|Move Value to Address Register
|
|-
|LS
|Move
|MOV.AA
|Move Address from Address Register
|
|-
|LS
|Move
|MOV.D
|Move Address to Data Register
|
|-
|LS
|Move
|MOVH.A
|Move High to Address
|
|-
|LS
|Move
|MTCR
|Move To Core Register
|
|-
|LS
|Arithmetic
|NE.A
|Not Equal Address
|
|-
|LS
|Arithmetic
|NEZ.A
|Not Equal Zero Address
|
|-
|LS
|Arithmetic
|NOP
|No Operation
|
|-
|LS
|Trap and Interrupt
|RESTORE
|Restore
|TC1.6
|-
| LS
|CSA Control Flow
|RET
|Return from Call
|
|-
|LS
|CSA Control Flow
|RFE
|Return From Exception
|
|-
|LS
|CSA Control Flow
|RFM
|Return From Monitor
|
|-
| LS
|CSA Control Flow
|RSLCX
|Restore Lower Context
|
|-
|LS
|Store
|ST.A
|Store Word from Address Register
|TC1.6*
|-
|LS
|Store
|ST.B
|Store Byte
|TC1.6*
|-
|LS
|Store
|ST.D
|Store Double-word
|
|-
|LS
|Store
|ST.DA
|Store Double-word from Address Registers
|
|-
| LS
|Store
|ST.H
|Store Half-word
|TC1.6*
|-
|LS
|Store
|ST.Q
|Store Half-word Signed Fraction
|
|-
|LS
|Store
|ST.T
|Store Bit
|
|-
|LS
|Store
|ST.W
|Store Word
|
|-
|LS
| Store
|STLCX
|Store Lower Context
|
|-
|LS
|Store
|STUCX
|Store Upper Context
|
|-
|LS
|Arithmetic
|SUB.A
|Subtract Address
|
|-
|LS
|CSA Control Flow
|SVLCX
|Save Lower Context
|
|-
|LS
|Load
|SWAP.W
|Swap with Data Register
|
|-
|LS
|Load
|SWAPMSK.W
|Swap under Mask
|TC1.6
|-
|LS
|CSA Control Flow
|SYSCALL
|System Call
|
|-
|LS
|Trap and Interrupt
|TRAPSV
|Trap on Sticky Overflow
|
|-
| LS
|Trap and Interrupt
|TRAPV
|Trap on Overflow
|
|-
|LS
| Trap and Interrupt
|WAIT
|Wait
|TC1.6
|-
|IP
| Arithmetic
|ABS
|Absolute Value
|
|-
|IP
|Arithmetic
|ABS.B
|Absolute Value Packed Byte
|
|-
|IP
|Arithmetic
|ABS.H
|Absolute Value Packed Half-word
|
|-
|IP
|Arithmetic
|ABSDIF
|Absolute Value of Difference
|
|-
|IP
|Arithmetic
|ABSDIF.B
|Absolute Value of Difference Packed Byte
|
|-
|IP
|Arithmetic
|ABSDIF.H
|Absolute Value of Difference Packed Half-word
|
|-
|IP
|Arithmetic
|ABSDIFS

|Absolute Value of Difference with Saturation
|
|-
|IP
|Arithmetic
|ABSDIFS.H
|Absolute Value of Difference Packed Half-word with Saturation
|
|-
|IP
|Arithmetic
|ABSS
|Absolute Value with Saturation
|
|-
| IP
|Arithmetic
|ABSS.H
|Absolute Value Packed Half-word with Saturation
|
|-
|IP
|Arithmetic
|ADD
|Add
|
|-
|IP
|Arithmetic
|ADD.B
|Add Packed Byte
|
|-
|IP
|Arithmetic
|ADD.H
|Add Packed Half-word
|
|-
|IP
| Arithmetic
|ADDC
|Add with Carry
|
|-
| IP
|Arithmetic
|ADDI
|Add Immediate
|
|-
|IP
|Arithmetic
|ADDIH
|Add Immediate High
|
|-
|IP
|Arithmetic
|ADDS
|Add Signed with Saturation
|
|-
|IP
|Arithmetic
|ADDS.H

|Add Signed Packed Half-word with Saturation
|
|-
|IP
|Arithmetic
|ADDS.HU
|Add Unsigned Packed Half-word with Saturation
|
|-
|IP
|Arithmetic
| ADDS.U
|Add Unsigned with Saturation
|
|-
|IP
|Arithmetic
|ADDX
|Add Extended
|
|-
|IP
|Logical
|AND
|Bitwise AND
|
|-
|IP
|Logical
|AND.AND.T
|Accumulating Bit Logical AND-AND
|
|-
|IP
|Logical
|AND.ANDN.T
|Accumulating Bit Logical AND-AND-Not
|
|-
|IP
|Logical
|AND.NOR.T
|Accumulating Bit Logical AND-NOR
|
|-
|IP
|Logical
|AND.OR.T
|Accumulating Bit Logical AND-OR
|
|-
| IP
|Logical
|AND.EQ
|Equal Accumulating
|
|-
|IP
|Logical
|AND.GE
|Greater Than or Equal Accumulating
|
|-
|IP
|Logical
|AND.GE.U
|Greater Than or Equal Accumulating Unsigned
|
|-
|IP
|Logical
|AND.LT
|Less Than Accumulating
|
|-
|IP
|Logical
| AND.LT.U
|Less Than Accumulating Unsigned
|
|-
|IP
|Logical
|AND.NE
|Not Equal Accumulating
|
|-
|IP
|Logical
|AND.T
|Bit Logical AND
|
|-
|IP
|Logical
|ANDN
|Bitwise AND-Not
|
|-
|IP
|Logical
|ANDN.T
| Bit Logical AND-Not
|
|-
|IP
|Coprocessor 0
|BMERGE
|Bit Merge
|
|-
|IP
|Coprocessor 0
|BSPLIT
|Bit Split
|
|-
|IP
|Arithmetic
|CADD
|Conditional Add
|
|-
|IP
|Arithmetic
|CADDN
|Conditional Add-Not
|
|-
|IP
|Count
|CLO
|Count Leading Ones
|
|-
|IP
|Count
|CLO.H
|Count Leading Ones in Packed Half-words
|
|-
|IP
| Count
|CLS
|Count Leading Signs
|
|-
|IP
|Count
|CLS.H
|Count Leading Signs in Packed Half-words
|
|-
|IP
|Count
|CLZ
|Count Leading Zeros
|
|-
|IP
|Count
|CLZ.H
|Count Leading Zeros in Packed Half-words
|
|-
|IP
|Move
|CMOV (16-bit)
|Conditional Move (16-bit)
|
|-
|IP
|Move
|CMOVN (16-bit)
|Conditional Move-Not (16-bit)
|
|-
|IP
|Coprocessor 0
| CRC32.B
|CRC32 Byte
|TC1.6.2
|-
|IP
|Coprocessor 0
|CRC32B.W {{rev|CRC32|TC1.6}}
|CRC32 Word Big-Endian
|TC1.6
|-
|IP
|Coprocessor 0
|CRC32L.W
|CRC32 Word Little-Endian
|TC1.6.2
|-
|IP
|Coprocessor 0
|CRCN
|User-Defined CRC
|TC1.6.2
|-
| IP
| Arithmetic
|CSUB
|Conditional Subtract
|
|-
|IP
|Arithmetic
|CSUBN
|Conditional Subtract-Not
|
|-
|IP
|Extract
|DEXTR
|Extract from Double Register
|
|-
|IP
|Integer Divide
|DVADJ
|Divide-Adjust
|
|-
|IP
|Integer Divide
|DIV
|Divide
|TC1.6
|-
|IP
|Integer Divide
|DIV.U
|Divide Unsigned
|TC1.6
|-
|IP
|Integer Divide
|DVINIT
|Divide-Initialization Word
|
|-
|IP
| Integer Divide
|DVINIT.U
|Divide-Initialization Word Unsigned

|
|-
|IP
|Integer Divide
| DVINIT.B
|Divide-Initialization Byte
|
|-
|IP
|Integer Divide
|DVINIT.BU
|Divide-Initialization Byte Unsigned
|
|-
|IP
|Integer Divide
|DVINIT.H
|Divide-Initialization Half-word
|
|-
|IP
|Integer Divide
|DVINIT.HU
|Divide-Initialization Half-word Unsigned
|
|-
|IP
|Integer Divide
|DVSTEP
|Divide-Step
|
|-
|IP
|Integer Divide
|DVSTEP.U
|Divide-Step Unsigned
|
|-
|IP
|Compare
|EQ
|Equal
|
|-
|IP
|Compare
|EQ.B
|Equal Packed Byte
|
|-
|IP
|Compare
|EQ.H
|Equal Packed Half-word
|
|-
|IP
|Compare
|EQ.W
|Equal Packed Word
|
|-
|IP
|Compare
|EQANY.B
|Equal Any Byte
|
|-
|IP
|Compare
|EQANY.H
|Equal Any Half-word
|
|-
|IP
|Extract
|EXTR
|Extract Bit Field
|
|-
|IP
|Extract
|EXTR.U

|Extract Bit Field Unsigned
|
|-
|IP
|Compare
|GE
|Greater Than or Equal
|
|-
| IP
|Compare
|GE.U
|Greater Than or Equal Unsigned
|
|-
|IP
|Extract
|IMASK
|Insert Mask
|
|-
|IP
|Extract
|INS.T
|Insert Bit
|
|-
|IP
|Extract
|INSN.T
|Insert Bit-Not
|
|-
|IP
| Extract
|INSERT
|Insert Bit Field
|
|-
|IP
|Coprocessor 0
|IXMAX
|Find Maximum Index
|
|-
|IP
|Coprocessor 0
|IXMAX.U
|Find Maximum Index (unsigned)
|
|-
|IP
|Coprocessor 0
|IXMIN
|Find Minimum Index
|
|-
|IP
|Coprocessor 0
|IXMIN.U
|Find Minimum Index (unsigned)
|
|-
|IP
|Control Flow
|JEQ
|Jump if Equal
|TC1.6*
|-
|IP
|Control Flow
|JGE
|Jump if Greater Than or Equal
|
|-
|IP
|Control Flow
|JGE.U
|Jump if Greater Than or Equal Unsigned
|
|-
|IP
|Control Flow
|JGEZ (16-bit)
|Jump if Greater Than or Equal to Zero (16-bit)
|
|-
|IP
|Control Flow
|JGTZ (16-bit)
|Jump if Greater Than Zero (16-bit)
|
|-
|IP
|Control Flow
|JLEZ (16-bit)
|Jump if Less Than or Equal to Zero (16-bit)
|
|-
|IP
|Control Flow
|JLT
|Jump if Less Than
|
|-
|IP
|Control Flow
|JLT.U
|Jump if Less Than Unsigned
|
|-
|IP
|Control Flow
|JLTZ (16-bit)
|Jump if Less Than Zero (16-bit)
|
|-
|IP
|Control Flow
|JNE
| Jump if Not Equal
|TC1.6*
|-
|IP
|Control Flow
|JNED
|Jump if Not Equal and Decrement
|
|-
|IP
|Control Flow
|JNEI
|Jump if Not Equal and Increment
|
|-
|IP
|Control Flow
|JNZ (16-bit)
| Jump if Not Equal to Zero (16-bit)
|
|-
|IP
|Control Flow
|JNZ.T
|Jump if Not Equal to Zero Bit
|
|-
|IP
|Control Flow
|JZ (16-bit)
| Jump if Zero (16-bit)
|
|-
| IP
|Control Flow
|JZ.T
|Jump if Zero Bit
|
|-
|IP
|Compare
|LT
|Less Than
|
|-
|IP
|Compare
|LT.U
|Less Than Unsigned
|
|-
|IP
|Compare
|LT.B

|Less Than Packed Byte
|
|-
|IP
|Compare
|LT.BU
|Less Than Packed Byte Unsigned
|
|-
|IP
|Compare
|LT.H
|Less Than Packed Half-word
|
|-
| IP
|Compare
|LT.HU
|Less Than Packed Half-word Unsigned
|
|-
|IP
|Compare
|LT.W
|Less Than Packed Word
|
|-
|IP
|Compare
|LT.WU
| Less Than Packed Word Unsigned
|
|-
| IP
|Multiply Accumulate
|MADD
|Multiply-Add
|
|-
|IP
|Multiply Accumulate
|MADDS
|Multiply-Add, Saturated
|
|-
|IP
|Multiply Accumulate
|MADD.H
|Packed Multiply-Add Q Format
|
|-
|IP
|Multiply Accumulate
|MADDS.H
|Packed Multiply-Add Q Format, Saturated
|
|-
|IP
|Multiply Accumulate
|MADD.Q
|Multiply-Add Q Format
|
|-
|IP
|Multiply Accumulate
|MADDS.Q
|Multiply-Add Q Format, Saturated
|
|-
|IP
|Multiply Accumulate
|MADD.U
|Multiply-Add Unsigned
|
|-
| IP
|Multiply Accumulate
|MADDS.U
|Multiply-Add Unsigned, Saturated
|
|-
|IP
|Multiply Accumulate
|MADDM.H
|Packed Multiply-Add Q Format Multi-precision
|
|-
|IP
|Multiply Accumulate
|MADDMS.H
|Packed Multiply-Add Q Format Multi-precision, Saturated
|
|-
|IP
|Multiply Accumulate
|MADDR.H
|Packed Multiply-Add Q Format with Rounding
|
|-
|IP
|Multiply Accumulate
|MADDRS.H
|Packed Multiply-Add Q Format with Rounding, Saturated
|
|-
|IP
|Multiply Accumulate
|MADDR.Q
|Multiply-Add Q Format with Rounding
|
|-
|IP
|Multiply Accumulate
|MADDRS.Q
|Multiply-Add Q Format with Rounding, Saturated
|
|-
|IP
|Multiply Accumulate
| MADDSU.H
|Packed Multiply-Add/Subtract Q Format
|
|-
|IP
|Multiply Accumulate
|MADDSUS.H
|Packed Multiply-Add/Subtract Q Format Saturated
|
|-
|IP
|Multiply Accumulate
|MADDSUM.H
|Packed Multiply-Add/Subtract Q Format Multi-precision
|
|-
|IP
|Multiply Accumulate
|MADDSUMS.H
|Packed Multiply-Add/Subtract Q Format Multi-precision Saturated
|
|-
|IP
|Multiply Accumulate
|MADDSUR.H
|Packed Multiply-Add/Subtract Q Format with Rounding
|
|-
|IP
|Multiply Accumulate
|MADDSURS.H
|Packed Multiply-Add/Subtract Q Format with Rounding Saturated
|
|-
|IP
| Arithmetic
|MAX
|Maximum Value
|
|-
|IP
|Arithmetic
|MAX.U
|Maximum Value Unsigned
|
|-
|IP
|Arithmetic
|MAX.B
|Maximum Value Packed Byte
|
|-
|IP
|Arithmetic
|MAX.BU
|Maximum Value Packed Byte Unsigned
|
|-
|IP
|Arithmetic
|MAX.H
|Maximum Value Packed Half-word
|
|-
|IP
|Arithmetic
|MAX.HU
|Maximum Value Packed Half-word Unsigned
|
|-
|IP
|Arithmetic
|MIN
|Minimum Value
|
|-
|IP
|Arithmetic
| MIN.U
|Minimum Value Unsigned
|
|-
|IP
|Arithmetic
|MIN.B
|Minimum Value Packed Byte
|
|-
|IP
|Arithmetic
|MIN.BU
|Minimum Value Packed Byte Unsigned
|
|-
|IP
|Arithmetic
|MIN.H
|Minimum Value Packed Half-word
|
|-
|IP
|Arithmetic
|MIN.HU
|Minimum Value Packed Half-word Unsigned
|
|-
|IP
|Move
|MOV
|Move
|
|-
|IP
|Move
|MOV.U
|Move Unsigned
|
|-
|IP
|Move
|MOVH
|Move High
|
|-
|IP
|Multiply Accumulate
|MSUB
|Multiply-Subtract
|
|-
|IP
|Multiply Accumulate
|MSUBS
|Multiply-Subtract, Saturated
|
|-
|IP
|Multiply Accumulate
|MSUB.H
|Packed Multiply-Subtract Q Format
|
|-
|IP
|Multiply Accumulate
|MSUBS.H
|Packed Multiply-Subtract Q Format, Saturated
|
|-
| IP
|Multiply Accumulate
|MSUB.Q
|Multiply-Subtract Q Format
|
|-
|IP
|Multiply Accumulate
|MSUBS.Q
|Multiply-Subtract Q Format, Saturated
|
|-
|IP
|Multiply Accumulate
|MSUB.U
|Multiply-Subtract Unsigned
|
|-
|IP
|Multiply Accumulate
|MSUBS.U
|Multiply-Subtract Unsigned, Saturated
|
|-
|IP
|Multiply Accumulate
|MSUBAD.H
|Packed Multiply-Subtract/Add Q Format
|
|-
|IP
| Multiply Accumulate
|MSUBADS.H
|Packed Multiply-Subtract/Add Q Format, Saturated
|
|-
|IP
|Multiply Accumulate
|MSUBADM.H
|Packed Multiply-Subtract/Add Q Format-Multi-precision
|
|-
|IP
|Multiply Accumulate
|MSUBADMS.H
|Packed Multiply-Subtract/Add Q Format-Multi-precision, Saturated
|
|-
|IP
|Multiply Accumulate
|MSUBADR.H
|Packed Multiply-Subtract/Add Q Format with Rounding
|
|-
|IP
|Multiply Accumulate
|MSUBADRS.H
|Packed Multiply-Subtract/Add Q Format with Rounding, Saturated
|
|-
| IP
|Multiply Accumulate
|MSUBM.H
|Packed Multiply-Subtract Q Format-Multi-precision
|
|-
|IP
|Multiply Accumulate
|MSUBMS.H
|Packed Multiply-Subtract Q Format-Multi-precision, Saturated
|
|-
|IP
|Multiply Accumulate
|MSUBR.H
|Packed Multiply-Subtract Q Format with Rounding
|
|-
|IP
|Multiply Accumulate
|MSUBRS.H
|Packed Multiply-Subtract Q Format with Rounding, Saturated
|
|-
|IP
|Multiply Accumulate
|MSUBR.Q
|Multiply-Subtract Q Format with Rounding
|
|-
|IP
|Multiply Accumulate
|MSUBRS.Q
|Multiply-Subtract Q Format with Rounding, Saturated
|
|-
|IP
|Multiply
|MUL
|Multiply
|
|-
|IP
|Multiply
|MULS
|Multiply, Saturated
|
|-
| IP
|Multiply
|MUL.H
|Packed Multiply Q Format
|
|-
|IP
| Multiply
|MUL.Q
|Multiply Q Format
|
|-
|IP
|Multiply
|MUL.U
|Multiply Unsigned
|
|-
|IP
|Multiply
|MULS.U
|Multiply Unsigned, Saturated
|
|-
|IP
|Multiply
|MULM.H
|Packed Multiply Q Format-Multi-precision
|
|-
|IP
|Multiply
|MULR.H
|Packed Multiply Q Format with Rounding
|
|-
|IP
|Multiply
|MULR.Q
|Multiply Q Format with Rounding
|
|-
|IP
|Logical
|NAND
|Bitwise NAND
|
|-
| IP
|Logical
|NAND.T
|Bit Logical NAND
|
|-
|IP
|Compare
|NE
|Not Equal
|
|-
|IP
|Logical
|NOR
|Bitwise NOR
|
|-
|IP
|Logical
|NOR.T
|Bit Logical NOR
|
|-
|IP
|Logical
|NOT (16-bit)
|Bitwise Complement NOT (16-bit)
|
|-
|IP
|Logical
|OR
|Bitwise OR
|
|-
|IP
|Logical
|OR.AND.T
|Accumulating Bit Logical OR-AND
|
|-
|IP
|Logical
|OR.ANDN.T
|Accumulating Bit Logical OR-AND-Not
|
|-
|IP
|Logical
|OR.NOR.T
|Accumulating Bit Logical OR-NOR
|
|-
|IP
|Logical
|OR.OR.T
|Accumulating Bit Logical OR-OR
|
|-
|IP
|Logical
|OR.EQ
|Equal Accumulating
|
|-
|IP
|Logical
|OR.GE
|Greater Than or Equal Accumulating
|
|-
|IP
|Logical
|OR.GE.U
|Greater Than or Equal Accumulating Unsigned
|
|-
|IP
|Logical
|OR.LT
|Less Than Accumulating
|
|-
|IP
|Logical
|OR.LT.U
|Less Than Accumulating Unsigned
|
|-
|IP
|Logical
|OR.NE
|Not Equal Accumulating
|
|-
|IP
|Logical
|OR.T
|Bit Logical OR
|
|-
|IP
| Logical
|ORN
|Bitwise OR-Not
|
|-
|IP
|Logical
|ORN.T
|Bit Logical OR-Not
|
|-
|IP
|Coprocessor 0
| PACK
|Pack
|
|-
|IP
|Coprocessor 0
|PARITY
|Parity
|
|-
|IP
|Count
|POPCNT.W
|Population Count Word
|TC1.6.2
|-
|IP
|Trap and Interrupt
|RSTV
|Reset Overflow Bits
|
|-
|IP
|Arithmetic
|RSUB
|Reverse-Subtract
|
|-
|IP
|Arithmetic
|RSUBS
|Reverse-Subtract with Saturation
|
|-
|IP
|Arithmetic
|RSUBS.U
|Reverse-Subtract Unsigned with Saturation
|
|-
|IP
|Arithmetic
|SAT.B
|Saturate Byte
|
|-
|IP
|Arithmetic
|SAT.BU
|Saturate Byte Unsigned
|
|-
|IP
|Arithmetic
|SAT.H
|Saturate Half-word
|
|-
|IP
|Arithmetic
|SAT.HU
|Saturate Half-word Unsigned
|
|-
|IP
|Arithmetic
|SEL
|Select
|
|-
|IP
|Arithmetic
|SELN
|Select-Not
|
|-
|IP
|Shift
|SH
|Shift
|
|-
|IP
|Shift
|SH.EQ
|Shift Equal
|
|-
|IP
|Shift
|SH.GE
|Shift Greater Than or Equal
|
|-
|IP
|Shift
|SH.GE.U
| Shift Greater Than or Equal Unsigned
|
|-
|IP
|Shift
|SH.H
|Shift Packed Half-words
|
|-
|IP
|Shift
|SH.LT
|Shift Less Than
|
|-
|IP
|Shift
|SH.LT.U
|Shift Less Than Unsigned
|
|-
|IP
|Shift
| SH.NE
|Shift Not Equal
|
|-
|IP
|Shift
|SH.AND.T
|Accumulating Shift-AND
|
|-
|IP
|Shift
|SH.ANDN.T
|Accumulating Shift-AND-Not
|
|-
|IP
|Shift
|SH.NAND.T
|Accumulating Shift-NAND
|
|-
|IP
|Shift
|SH.NOR.T
|Accumulating Shift-NOR
|
|-
|IP
|Shift
|SH.OR.T
|Accumulating Shift-OR
|
|-
|IP
|Shift
|SH.ORN.T
|Accumulating Shift-OR-Not
|
|-
|IP
|Shift
|SH.XNOR.T
|Accumulating Shift-XNOR
|
|-
|IP
|Shift
|SH.XOR.T
|Accumulating Shift-XOR
|
|-
|IP
|Shift
|SHA
|Arithmetic Shift
|
|-
|IP
|Shift
|SHA.H
|Arithmetic Shift Packed Half-words
|
|-
|IP
|Shift
|SHAS
|Arithmetic Shift with Saturation
|
|-
|IP
|Arithmetic
|SHUFFLE
|Byte Shuffle
|TC1.6.2
|-
|IP
|Arithmetic
|SUB
|Subtract
|
|-
|IP
|Arithmetic
|SUB.B
|Subtract Packed Byte
|
|-
|IP
|Arithmetic
|SUB.H
|Subtract Packed Half-word
|
|-
|IP
|Arithmetic
|SUBC
| Subtract With Carry
|
|-
|IP
|Arithmetic
|SUBS
|Subtract Signed with Saturation
|
|-
|IP
|Arithmetic
|SUBS.U
|Subtract Unsigned with Saturation
|
|-
|IP
|Arithmetic
|SUBS.H
| Subtract Packed Half-word with Saturation
|
|-
|IP
|Arithmetic
|SUBS.HU
|Subtract Packed Half-word Unsigned with Saturation
|
|-
|IP
|Arithmetic
|SUBX
|Subtract Extended
|
|-
|IP
|Coprocessor 0
|UNPACK
|Unpack Floating Point
|
|-
|IP
|Logical
|XNOR
|Bitwise XNOR
|
|-
|IP
|Logical
|XNOR.T
|Bit Logical XNOR
|
|-
|IP
|Logical
|XOR
|Bitwise XOR
|
|-
|IP
|Logical
|XOR.EQ
| Equal Accumulating
|
|-
|IP
|Logical
|XOR.GE
|Greater Than or Equal Accumulating
|
|-
|IP
|Logical
|XOR.GE.U
|Greater Than or Equal Accumulating Unsigned
|
|-
|IP
|Logical
|XOR.LT
|Less Than Accumulating
|
|-
|IP
|Logical
|XOR.LT.U
|Less Than Accumulating Unsigned
|
|-
|IP
|Logical
|XOR.NE
|Not Equal Accumulating
|
|-
|IP
|Logical
|XOR.T
|Bit Logical XOR
|
|-
|FPU
|Floating Point
|ADD.F
|Add Float
|
|-
|FPU
|Floating Point
|CMP.F
|Compare Float
|
|-
|FPU
|Floating Point
|DIV.F
|Divide Float
|
|-
| FPU
|Floating Point
|FTOI
|Float to Integer
|
|-
|FPU
|Floating Point
|FTOIZ
|Float to Integer, Round towards Zero
|TC1.3.1
|-
|FPU
|Floating Point
|FTOQ31
|Float to Fraction
|
|-
|FPU
|Floating Point
|FTOQ31Z
|Float to Fraction, Round towards Zero
| TC1.3.1
|-
|FPU
|Floating Point
|FTOU
|Float to Unsigned
|
|-
|FPU
|Floating Point
|FTOUZ
|Float to Unsigned, Round towards Zero
|TC1.3.1
|-
|FPU
|Floating Point
|FTOHP
|Single Precision to Half Precision
|TC1.6.2
|-
|FPU
|Floating Point
|HPTOF
|Half Precision to Single Precision
| TC1.6.2
|-
|FPU
|Floating Point
|ITOF
|Integer to Float
|
|-
|FPU
|Floating Point
|MADD.F
|Multiply Add Float
|
|-
|FPU
|Floating Point
| MSUB.F
|Multiply Subtract Float
|
|-
|FPU
|Floating Point
|MUL.F
|Multiply Float
|
|-
|FPU
|Floating Point
|Q31TOF
|Fraction to Floating-point
|
|-
|FPU
|Floating Point
|QSEED.F
|Inverse Square Root Seed
|
|-
|FPU
|Floating Point
|SUB.F
|Subtract Float
|
|-
|FPU
|Floating Point
|UPDFL
|Update Flags
|
|-
|FPU
|Floating Point
|UTOF
|Unsigned to Floating-point
|
|}

==Comparison with Other Microcontroller Architectures ==
In the automotive and industrial MCU landscape, Infineon’s TriCore™/AURIX™ architecture stands alongside other major architectures such as ARM Cortex-based microcontrollers, Power Architecture (PowerPC) based controllers, and more recently RISC-V based designs. '''Architecturally''', TriCore’s™ niche is its unified MCU/DSP design and native multicore safety support. In contrast, many competitors historically used separate cores or accelerators for DSP tasks (for example, ARM’s Cortex-M4/M7 cores include a DSP instruction set, but earlier automotive designs often combined a CPU with a separate DSP or relied on fixed-function accelerators). TriCore™ was one of the first to meld DSP capabilities into a general-purpose controller core<ref name="ref19484776952">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>, giving it an edge in signal-processing-heavy automotive tasks like ignition control or motor control. Moreover, AURIX™ introduced multi-core lockstep and distributed memory protection at a time when many automotive MCU competitors were still single-core or dual-core. For instance, Texas Instruments’ '''Hercules''' safety microcontrollers use dual ARM Cortex-R4 cores in lockstep to achieve similar fault-detection as AURIX’s™ lockstep pairs, and NXP (Freescale)’s older PowerPC-based MCUs implemented lockstep on a single core pair. AURIX’s™ approach with up to three lockstep pairs (in a 2oo3 or 1oo2D configuration) on one chip was relatively unique, enabling higher ASIL-D performance within one device<ref name="ref19519075552">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref>. In terms of '''raw performance''', TriCore™ cores at 300 MHz deliver comparable DMIPS/MHz to high-end ARM Cortex-R and Cortex-M cores. A 300 MHz TriCore™ 1.6.2 is roughly in the same class as a 300 MHz ARM Cortex-R5 or a 350 MHz Cortex-M7 in terms of Dhrystone performance, although specific benchmarks vary<ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref><ref name="ref1077685626">Aurix TC3xx microcontroller - how to access shared variables from ... https://www.reddit.com/r/embedded/comments/10v8vtz/aurix_tc3xx_microcontroller_how_to_access_shared/</ref>. The AURIX TC3xx’s hexa-core design can outpace many dual- or triple-core competitors on aggregate throughput, though ARM-based families have also scaled up core counts in some SoC-like designs.

When comparing '''security features''', Infineon’s decision to include a high-grade HSM on AURIX™ gave it a head start in automotive cybersecurity. ARM’s TrustZone technology (available on some Cortex-M35/M33 and higher cores) provides a form of security partitioning, but it’s not directly equivalent to a full HSM with its own CPU and crypto engine. Many automotive MCU vendors (like NXP and ST) have since incorporated dedicated security modules or accelerators in their ARM-based designs, but AURIX’s™ HSM (with EVITA High compliance) remains a standout for handling features like onboard encryption, secure boot, and even V2X cryptography without external chips<ref name="ref20223578062">UDE Debug, Trace and Test solutions for Infineon TriCore™ AURIX™ TC32, TC33, TC35, TC36, TC37, TC38, TC39, TC3x Microcontrollers https://www.pls-mc.com/products/infineon-tricore-aurix-tc32-tc33-tc35-tc36-tc37-tc38-tc39-microcontrollers/</ref>. On the other hand, the broader ecosystem for '''software and tools''' tends to favor ARM. ARM Cortex-based microcontrollers benefit from widespread compiler support, development tools, and a large developer community. Infineon’s TriCore™, being proprietary, has a more specialized toolchain (with commercial compilers from Tasking, HighTec, etc., and a smaller community), which can mean a higher barrier to entry for new developers. However, automotive Tier-1 suppliers have invested in TriCore™ toolchains for years, and Infineon provides AUTOSAR libraries and MCAL drivers that ease development in the automotive context<ref name="ref496771205">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref>.

In terms of '''industry adoption''', TriCore™/AURIX™ has become one of the dominant architectures in European automotive electronics, often chosen for its safety and performance in powertrain and safety domains, while ARM-based microcontrollers have gained popularity especially in body electronics and new ECU designs due to their flexibility and the ARM ecosystem. Historically, high-end automotive MCUs were based on PowerPC cores (like NXP/Freescale MPC5xx/MPC55xx) or proprietary cores like Renesas V850/RH850. Infineon’s AURIX™ emerged as a strong competitor to these, offering a new option with multicore and DSP advantages. By the mid-2010s, ARM made inroads into this space (TI’s TMS570/Hercules with Cortex-R4, and later NXP and Renesas adopting ARM Cortex-R/M for some families), but many automotive OEMs continued to trust established platforms. A 2013 analysis noted that PowerPC was dominant, with Infineon’s TriCore™ and Renesas’s V850 as big competitors, and ARM as a “latest entrant” in the automotive MCU arena. Since then, ARM cores have seen increasing use in automotive for domains like gateways and ADAS (e.g., NVIDIA and Mobileye use ARM in their SoCs, and some microcontroller families like Cypress Traveo and NXP S32K are ARM-based), but AURIX™ maintains a significant share in high safety integrity applications.<ref name="ref196337548">Automotive world: PowerPC vs ARM vs V850 vs SH - Page 1 https://www.eevblog.com/forum/microcontrollers/automotive-world-powerpc-vs-arm-vs-v850-vs-sh/</ref>

Looking forward, the rise of '''RISC-V''' open architecture presents both a competition and an opportunity. Infineon itself has announced that it will introduce a new AURIX™ family branch that includes RISC-V cores alongside TriCore™<ref name="ref13290563422">Infineon brings RISC-V to the automotive industry and is first to announce an automotive RISC-V microcontroller family – RISC-V International https://riscv.org/ecosystem-news/2025/03/infineon-brings-risc-v-to-the-automotive-industry-and-is-first-to-announce-an-automotive-risc-v-microcontroller-family/</ref>. This reflects a trend toward heterogeneous architectures: pairing a proven safety-critical core (TriCore™) with supplementary cores that can be optimized for tasks like AI acceleration or network management. RISC-V’s open ecosystem could bring more developers and third-party IP into the fold, potentially addressing the ecosystem gap between TriCore™ and ARM. Other companies are also exploring RISC-V for automotive; for example, Western Digital and GreenWaves have automotive-oriented RISC-V processors, and some start-ups are aiming for ASIL-rated RISC-V cores. However, as of the TC3xx generation, AURIX’s™ competition remains largely the ARM Cortex-R5-based MCUs (like Renesas RH850/U2x series which moved to ARM cores, or NXP’s S32S which uses Cortex-R52) and the last of the line PowerPC-based units. In '''summary''', AURIX’s™ TriCore™ architecture distinguishes itself with a laser focus on automotive needs – blending real-time control, DSP, built-in redundancy, and security in one package – whereas ARM architectures offer a broad general-purpose approach with wide support, and RISC-V is emerging as a flexible, open alternative. Each has its strengths: AURIX™ for integrated safety/security, ARM for its ubiquity and IP ecosystem, and RISC-V for customizability. Infineon’s strategy indicates a recognition that future architectures may combine these strengths to meet the ever-growing demands of software-defined vehicles<ref name="ref13290563422" />.
==See Also==

*[[Infineon AURIX TC2xx]]
*[[Infineon AURIX TC3xx]]
*[[Infineon AURIX TC4x]]

==External Links==

*[https://www.infineon.com/dgdl/TC1_3_ArchOverview_1.pdf?fileId=db3a304312bae05f0112be86204c0111 TriCore™ 1.3 Architecture Overview Handbook]
*[https://www.infineon.com/dgdl/tc_v131_corearchitecture_v__138.pdf?fileId=db3a304412b407950112b409c4500359 TriCore® TC1.3 & TC1.3.1 User Manual Volume 1 - Core Architecture]
*[https://www.infineon.com/dgdl/Infineon-TC2xx_Architecture_vol1-UM-v01_00-EN.pdf?fileId=5546d46269bda8df0169ca1bea3624a5 TriCore® TC1.6P & TC1.6E User Manual Volume 1 - Core Architecture]
*[https://www.infineon.com/dgdl/Infineon-TC2xx_Architecture_vol2-UM-v01_00-EN.pdf?fileId=5546d46269bda8df0169ca1bf33124a8 TriCore® TC1.6P & TC1.6E User Manual Volume 2 - Instruction Set]
*[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd TriCore™ TC1.6.2 User Manual Volume 1 - Core Architecture]
*[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 TriCore™ TC1.6.2 User Manual Volume 2 - Instruction Set]

==References==
<references />
[[Category:Supported Architectures]]

Infineon AURIX TC4x Parallel Processing Unit (PPU)

2025-04-08T08:11:47Z

Mira.steinmetz:

The '''Parallel Processing Unit (PPU)''' in [[Infineon AURIX TC4x|Infineon’s AURIX™ TC4x]] microcontroller family is a specialized co-processor designed to accelerate highly parallel computations for automotive and industrial applications. It complements the TC4x’s [[TriCore Instruction Set Architecture|TriCore™ 1.8]] CPUs by offloading computationally intensive tasks such as digital signal processing and neural network inference, enabling artificial intelligence (AI) capabilities up to the highest automotive safety levels (ASIL-D). The PPU features a vector processing architecture and dedicated hardware accelerators, allowing it to execute math-intensive algorithms in parallel and in real time, which is critical for advanced driver assistance systems (ADAS), electric powertrain control, and other safety-critical functions.<ref name="ref1001512215">32-bit TriCore™ AURIX™– TC4x - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc4x/</ref>

== Overview ==

Infineon’s AURIX™ TC4x is the third-generation family of 32-bit automotive microcontrollers, built for safe and secure real-time processing in domains such as powertrain, chassis, advanced safety, and ADAS. The TC4x family integrates up to six TriCore™ v1.8 CPU cores (with lockstep redundancy for safety) and a suite of specialized accelerators to meet the increasing performance demands of modern vehicles. Among these new accelerators is the '''Parallel Processing Unit (PPU)''' – a new programmable vector co-processor introduced in the TC4x family to boost signal processing and AI performance. The PPU’s role is to handle tasks that involve large amounts of numeric computation or data parallelism, thereby augmenting the microcontroller’s throughput while maintaining deterministic real-time behavior needed for automotive applications.<ref name="ref1047817100">Lauterbach supports Infineon’s Next-Generation AURIX™ TC4x https://www.lauterbach.com/press-releases/lauterbach-announces-debug-and-trace-support-for-infineons-next-generation-aurix-microcontrollers</ref><ref name="ref1001512215"/>

Designed as a '''heterogeneous multi-core architecture''', the AURIX™ TC4x combines conventional scalar processing cores with the PPU vector core and other accelerators. This approach allows the system to offload specialized workloads to the appropriate processing unit. For example, time-critical control tasks and general application code run on the TriCore CPUs, while the PPU is invoked for high-volume data processing like sensor data filtering, complex control algorithms, or neural network evaluation. By relieving the main CPUs of these heavy workloads, the PPU helps the TC4x family achieve significantly higher performance (up to 78× in certain benchmarks compared to a single TriCore 1.8 core) without compromising the strict safety and real-time requirements of automotive systems.<ref name="ref1239294738">Software Support for Parallel ADAS Applications on Pre-development Version of the Aurix TC4, Master Thesis, Bc. Lukáš Bielesch https://dspace.cvut.cz/bitstream/handle/10467/101423/F3-DP-2022-Bielesch-Lukas-bieleluk_thesis_final.pdf?sequence=-1&isAllowed=y</ref><ref name="ref1315913395">empower® is the addin for PowerPoint presentations https://www.infineon.com/dgdl/Infineon_AURIX_TC4x.pdf?fileId=8ac78c8b7e4b5364017e4e1a407c0001</ref>

== Architecture ==

=== Core Design and Instruction Set ===

The PPU is implemented as a '''vector processor''' based on the Synopsys DesignWare ARC EV71 architecture. It consists of a 32-bit RISC processing core coupled with a wide Single-Instruction Multiple-Data (SIMD) vector unit. The PPU’s vector unit features 512-bit vector registers and executes instructions that operate on multiple data elements in parallel. In essence, a single vector instruction can perform the same operation across an entire array of values (for example, multiplying 16 or more data points at once), which contrasts with the scalar TriCore CPUs that execute one operation on one set of operands at a time. This vectorized design, common in digital signal processors (DSPs), enables significantly higher throughput for algorithms that can be parallelized, such as signal filtering, matrix operations, and image processing.<ref name="ref1239294738"/><ref name="ref504569965">Synopsys ARC MetaWare Toolkit for Infineon AURIX TC4x https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware-aurix</ref><ref name="ref1696196978">#ev #electricvehicles #emobility #electrification #electronics #ai | EV Tech Insider https://www.linkedin.com/posts/evtechinsider_ev-electricvehicles-emobility-activity-7259210423105671168-fP1b</ref>

=== Memory Model and Parallelism ===

The PPU operates within the microcontroller’s memory space as a peer processor alongside the TriCore CPUs. It is equipped with its own local memory hierarchy (including instruction and data caches or tightly coupled memories) and connects to the shared memory via the on-chip interconnect fabric. A '''Data Routing Engine (DRE)''' is included in the TC4x architecture to facilitate efficient data movement between the PPU, main memory, and other peripherals. This helps feed the PPU with data (for example, sensor readings or large data buffers) and retrieve results with minimal CPU intervention. The PPU can also use direct memory access (DMA) to autonomously fetch and store data to shared memory, ensuring that data transfers occur in parallel with computation.<ref name="ref1239294738"/><ref name="ref1001512215"/>

To support parallel processing without interfering with the real-time tasks on the TriCore cores, the PPU and CPU cores communicate through well-defined mechanisms. Shared memory regions and '''mailbox registers''' allow exchange of data and signals between the scalar cores and the PPU. '''Inter-core interrupts''' are used for synchronization and job control – for instance, a TriCore core can signal the PPU to start processing a dataset, or the PPU can interrupt a CPU when it has finished a computation task. This architecture enables true parallelism at the system level: while the PPU crunches numbers on a vectorizable task, the main CPUs can continue executing other software tasks. The net effect is a form of coarse-grained parallel processing (different cores executing different tasks concurrently) combined with the fine-grained data parallelism within the PPU itself. The PPU’s vector unit executes SIMD operations across up to 512-bit wide data sets, and its internal design can be configured to handle various data widths (such as 8, 16, or 32-bit elements) in parallel. This flexibility allows tuning for either higher precision or higher parallel count, as needed by the application.<ref name="ref1239294738"/><ref name="ref1466902521">Synopsys EV7x Vision Processors https://www.synopsys.com/dw/ipdir.php?ds=ev7x-vision-processors</ref>

== Hardware Acceleration and Applications ==

[[File:PPU Applications.jpg|thumb|''Illustrative range of PPU application domains and tasks. The PPU can handle high-frequency control loops (on the order of microseconds) for power electronics as well as more complex, slower tasks such as sensor fusion and AI-based predictive control. It supports both observer-based control algorithms and neural network–based functions across automotive use cases'' <ref name="ref623706068" />]]
The PPU provides significant hardware acceleration for computations common in automotive and industrial systems. Its vector DSP engine is capable of '''high-throughput signal processing'''. In practical terms, the PPU can execute complex math such as fast Fourier transforms, digital filters, matrix multiplications, and trigonometric calculations much faster than the general-purpose TriCore CPUs by leveraging its 512-bit SIMD instructions. This is especially beneficial for applications like radar signal processing or sensor data fusion, where large matrices or arrays of data must be processed under tight time constraints.<ref name="ref623706068">New PPU SIMD vector DSP - Infineon Technologies https://www.infineon.com/cms/en/product/promopages/new-ppu-simd-vector-dsp/</ref><ref name="ref1239294738"/>

The '''automotive applications''' of the PPU span a wide range of domains:
* '''eMobility and power control:''' In electric vehicles, the PPU can be used in on-board chargers, DC/DC converters, and traction motor inverters to perform high-bandwidth control algorithms and complex calculations for power conversion efficiency and motor control. For example, field-oriented control of motors involves heavy linear algebra and trigonometric computations that the PPU can accelerate. It also enables advanced battery management system (BMS) functions like state-of-charge (SoC) and state-of-health (SoH) estimation using adaptive algorithms or even neural networks.<ref name="ref623706068"/>
* '''Advanced Driver Assistance Systems (ADAS):''' The PPU supports use cases in radar signal processing, lidar, and sensor fusion for ADAS. It can process raw data from radar sensors using fast DSP operations or run a neural network to identify objects in sensor data, all within the tight latency required for functions like automatic emergency braking or lane-keeping. Its high parallel throughput is advantageous for handling the massive data streams from high-resolution sensors in real time.<ref name="ref623706068"/>
* '''Domain and zone controllers:''' Future vehicle E/E architectures often involve domain controllers (for vehicle dynamics, chassis control, etc.) or zonal controllers that handle multiple functions. The PPU is suited for '''domain control tasks''' such as predictive vehicle motion control, complex vehicle dynamics simulations, or coordinating multiple sensor inputs. It enables these controllers to implement sophisticated algorithms (like model-predictive control or AI-based sensor calibration) that require intensive computation, thereby increasing the accuracy and responsiveness of systems like stability control or autonomous driving logic.<ref name="ref623706068"/>
* '''Safety and monitoring features:''' Even tasks like '''siren sound detection''' (acoustic pattern recognition for emergency vehicle detection) or other audio signal processing in the vehicle can leverage the PPU’s DSP capability. Similarly, the PPU can assist with cybersecurity or functional safety monitoring algorithms that may use heavy mathematics (for example, cryptographic filtering or redundancy checks) by accelerating those computations in parallel.<ref name="ref1167709857">AURIX™ TC4x microcontrollers for embedded AI application development receive safety assessment from Fraunhofer IKS - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2024/INFATV202404-093.html</ref><ref name="ref1001512215"/>

While the AURIX™ TC4x and its PPU are primarily aimed at automotive, many of these capabilities are equally valuable in '''industrial applications'''. Industrial control systems (such as robotics controllers, industrial drives, or renewable energy inverters) have similar demands for real-time, high-throughput computations. The PPU’s hardware acceleration of control algorithms and neural network inference can enable smarter factory automation, high-performance motor drives, and safety systems in industrial settings. Furthermore, the compliance of the TC4x platform with automotive safety standards (ISO 26262 ASIL-D) corresponds to SIL 3 capability under IEC 61508 for industrial use, making the PPU-equipped microcontrollers attractive for safety-critical industrial controllers as well.<ref name="ref1899712745">AURIX TC4x: Safety Solutions from HighTec - HighTec EDV-Systeme GmbH https://hightec-rt.com/products/aurix-tc4x-safety-solutions</ref>

== Integration with the TC4x Platform ==

The PPU is tightly integrated into the AURIX™ TC4x system-on-chip alongside the TriCore CPU clusters and other accelerators. It functions as a '''co-processor''', with a level of autonomy in executing its own instruction stream, yet it shares the overall memory map and resources of the microcontroller. The integration is designed such that the PPU can be treated as another compute core in the system, managed by the system software when needed. For example, the TC4x platform includes an AUTOSAR-compatible '''Complex Device Driver (CDD)''' for the PPU, which allows automotive software (running on a TriCore) to dispatch tasks to the PPU and manage its operation in a controlled manner. A runtime component often called the ''PPU dispatcher'' is provided to queue and schedule parallel tasks on the PPU, handle the initiation of PPU execution, and retrieve results when finished. This dispatcher abstracts the details of PPU job control from the application, so developers can request computations (like “perform this FFT” or “run this neural network on new data”) and the system will utilize the PPU to complete them asynchronously.<ref name="ref504569965"/>

From a hardware perspective, the PPU connects to the microcontroller’s internal buses and interconnects. Shared SRAM memory is accessible to both the TriCore cores and the PPU, enabling bulk data to be passed by reference rather than copied between cores. For instance, a TriCore core can populate a buffer with sensor data in shared memory and then signal the PPU to process it, rather than explicitly feeding each data point. The '''Data Routing Engine (DRE)''' further assists in shuttling data between the PPU and other subsystems efficiently. In addition, mutual exclusion and memory protection mechanisms ensure that the PPU’s operations do not interfere with the timing and memory of the main CPUs. Infineon’s architecture implements safeguards so that even though the PPU shares buses and memory, critical real-time tasks on the TriCore (such as an interrupt service routine for safety) can preempt bus access if needed to maintain determinism (this falls under the TC4x’s overall ''freedom-from-interference'' design philosophy for mixed-criticality systems).<ref name="ref1001512215"/>

'''Inter-core communication''' is achieved through interrupts and handshaking flags. The TriCore CPUs can start or stop the PPU, and the PPU can interrupt the main CPUs upon task completion or if it needs attention. Software mailboxes (basically designated memory or register locations) are typically used to post job descriptors or status flags between the cores. This design is similar to a heterogeneous multi-processor system where a host CPU controls an accelerator: the host sets up the data and parameters for the accelerator, triggers it, and later reads back the results. In TC4x, however, all of this happens on a single chip and within a unified development environment, making the use of the PPU relatively seamless for developers familiar with multi-core programming.<ref name="ref1239294738"/>

Notably, the PPU is '''independent of the TriCore CPU architecture''' – it does not execute TriCore instructions and vice versa. Instead, it runs its own code (compiled for the ARC EV71 ISA) from either internal code memory or system memory. Tools like debuggers have been updated to be aware of this extra core. For example, Lauterbach’s TRACE32 debugging tool can simultaneously debug all TriCore CPUs ''and'' the PPU and trace their execution in parallel. This full-system visibility is important when integrating PPU tasks into the application, since developers need to coordinate and verify the interaction between the main application and the parallel routines on the PPU.<ref name="ref1047817100"/>

== Real-Time and Safety Considerations ==

A critical aspect of the AURIX™ TC4x PPU is that it is designed to meet the stringent '''real-time and functional safety requirements''' of automotive systems. In terms of real-time behavior, the PPU’s operations are deterministic and can be analyzed for worst-case execution time, which is essential for ensuring it fits within the timing budgets of safety-critical tasks. The use of hardware acceleration means that tasks that would otherwise take an impractically long time on a CPU (potentially causing deadline misses) can be completed much faster on the PPU, often turning minutes of CPU processing into milliseconds or less. This allows sophisticated algorithms (like high-order filters or deep neural networks) to be used in real-time control loops where previously they would have been too slow. System designers can assign PPU-heavy tasks lower priorities or schedule them in parallel so that the main control loop on a TriCore is never delayed waiting for the PPU; instead, results are ready when needed. The TC4x architecture also supports features like CPU and bus virtualization to ensure that even when multiple cores (TriCore and PPU) are active, critical tasks maintain their timing (for example, through quality-of-service controls on memory accesses).<ref name="ref1315913395"/><ref name="ref1047817100"/>

From a safety perspective, Infineon has built the PPU and TC4x as '''ASIL-D compliant''' components, meaning they can be used in systems that require the highest level of automotive safety integrity. The PPU hardware is likely implemented with various safety mechanisms: its internal memories (register files, caches) and buses have error-correction (ECC) to detect and correct bit flips; the logic may have built-in self-test routines and fault diagnostics that run at startup or periodically to ensure the PPU is operating correctly. Infineon and Synopsys also offer a ''functional safety variant'' of the ARC EV processor (EV71FS) which would include safety extensions such as lockstep comparators or redundant computation for critical parts. These measures enable the PPU to detect internal faults and either correct them or report them to the safety monitors in the system, so that a proper safe state can be achieved if a malfunction occurs. The overall TC4x microcontroller includes a safety management unit that supervises all cores (TriCore and PPU alike) and can, for example, reset or isolate a core that behaves unexpectedly.<ref name="ref1001512215"/><ref name="ref1167709857"/><ref name="ref542420283">[PDF] Synopsys Processor Solutions https://www.synopsys.com/dw/doc.php/ds/cc/dw-processor-solutions.pdf</ref><ref name="ref1080637602">[PDF] Software Support for Parallel ADAS Applications on Pre ... https://dspace.cvut.cz/bitstream/handle/10467/101423/F3-DP-2022-Bielesch-Lukas-bieleluk_thesis_final.pdf?sequence=-1&isAllowed=y</ref>

The '''SAFE AI''' initiative is an example of how the PPU’s capabilities are being qualified for safety. In 2024, Fraunhofer IKS assessed the AURIX™ TC4x family with its PPU for the safe deployment of AI in automobiles. The result was that the PPU, as an AI accelerator, meets the necessary safety and robustness criteria for using machine learning in safety-critical systems. This is significant because AI algorithms (like neural networks) are typically seen as black boxes, but with the PPU, their execution becomes deterministic and monitorable enough to be included in an ASIL-D system. By adhering to safety frameworks (such as ISO 26262 and the emerging ISO/PAS 8800 for AI), the PPU allows automotive engineers to leverage complex AI models for tasks like sensor interpretation or anomaly detection ''while still complying with safety standards''. In conjunction with redundant sensing and cross-checking (e.g., comparing an AI-based output with a simpler physics-based calculation as a plausibility check), the PPU’s use can increase both the intelligence and safety of automotive systems.<ref name="ref1167709857"/>

In summary, the Infineon AURIX™ TC4x PPU is a pivotal addition to the microcontroller family’s architecture, marrying high performance parallel processing with the rigorous demands of real-time, safety-critical operation. It enables a new class of in-vehicle computations – from high-fidelity motor control to embedded deep learning – all within the envelope of an automotive-qualified, single-chip solution. This combination of capabilities makes the TC4x PPU a key enabler for the next generation of automotive and industrial innovations that require both '''computational muscle and uncompromising safety'''.

== See Also ==

* [[TriCore Instruction Set Architecture]]
* [[Infineon AURIX TC4x]]
* [[emmtrix Code Vectorizer]]

== References ==

<references/>
[[Category:Supported Architectures]]

emmtrix Code Vectorizer

2025-04-08T08:07:40Z

Mira.steinmetz:

emmtrix Code Vectorizer is a C source-to-source compiler that vectorizes C code for various SIMD architectures like [[Infineon AURIX TC4x|Infineon AURIX TC4x PPU]], x86 AVX, ARM NEON, or RISC-V V extensions. It follows an semi-automatic approach, where the user can guide the vectorization process from an Eclipse-based GUI or by using pragmas in the C code. The vectorized C code is always visible to the user, which makes it easy to follow the transformation and to understand the generated code. The generated code can be compiled with the vendor’s compiler and either run on the target hardware or in a simulator to get performance feedback and verify the correctness of the transformation.

=== Multi-Precision Vector Math Library ===
The emmtrix Code Vectorizer incorporates a multi-precision vector math library that provides vectorized implementations of common C mathematical functions like sinf, cosf, expf, logf, powf, sqrtf, tanhf and many more. The library provides multiple versions of each function to provide the best trade-off between accuracy and performance. During vectorization, the vector math library is used to replace scalar math functions with vectorized versions. By specifying the accuracy requirements in [[ULP Difference of Float Numbers|ULPs (units in the last place)]], the user can control which version of the function is used.
{| class="wikitable"
|-
! Function
!Info
! Accuracy<ref>Accuracy of hardware version are given from the data sheet. A ULP 0.0 means that the implementation is exact. Otherwise, the highest know ULP is provided. Math functions that are based on non-perfect hardware implementation use a pessimistic software implementation for ULP evaluation. A more accurate ULP evaluation could be provided on request.</ref> [ULP]
! Latency on AURIX™ TC4x [cycles]
! Throughput on AURIX™ TC4x [cycles]
|-
|fabsf
|
|0.0
|
|
|-
|fminf
|
|0.0
|
|
|-
|fmaxf
|
|0.0
|
|
|-
|roundf
|
|0.0
|11
|5
|-
|ceilf
|
|0.0
|6
|4
|-
|floorf
|
|0.0
|6
|4
|-
|truncf
|
|0.0
|6
|4
|-
| sqrtf
|Hardware version
| 0.5
|16
|7
|-
| expf
|Hardware version
| 1.0
|11
|6
|-
|exp2f
|Hardware version
|1.0
|14
|6
|-
| log2f
|Hardware version
| 1.0
|14
|6
|-
|logf
|Based on log2f ULP 1.0 hardware version
|1.93
|
|
|-
|log10f
|Based on log2f ULP 1.0 hardware version
|2.50
|
|
|-
| sinf
|Hardware version
| 1.0
|14
|6
|-
| cosf
|Hardware version
| 1.0
|14
|6
|-
|tanf
|Based on sinf/cosf ULP 1.0 hardware version
|3.42
|
|
|-
| rowspan="4" | tanhf
| rowspan="4" |Based on expf ULP 1.0 hardware version
|7.08
|41
|18
|-
|4.23
|41
|19
|-
|2.74
|41
|23
|-
|1.91
|41
|27
|-
|hypotf
|Based on sqrt ULP 0.5 hardware vesrion
|1.995
|
|
|-
|remainderf
|
|
|
|
|-
|fmodf
|
|
|
|
|-
|fdimf
|
|
|
|
|}
[[Category:emmtrix Tools]]
<references />
[[Category:Math Function Accuracy]]

Infineon AURIX TC4x

2025-04-08T08:05:30Z

Mira.steinmetz:

[[File:Infineon Aurix TC4x.webp|right|frameless]]
The TC4x is Infineon's latest generation of AURIX™ microcontrollers, designed for advanced automotive applications, including eMobility, Advanced Driver Assistance Systems (ADAS), and automotive E/E (Electric/Electronic) architectures. These microcontrollers are built on a 28 nm process and feature the [[TriCore Instruction Set Architecture|TriCore™ 1.8 instruction set architecture]], which includes up to six cores running at speeds up to 500 MHz. This architecture is optimized for high-performance and real-time applications.

== Key Features ==
* '''High Performance and Scalability''': Equipped with a Parallel Processing Unit (PPU), Data Routing Engine (DRE), and other accelerators to enhance AI capabilities and real-time processing.
* '''Extensive Connectivity''': Supports high-speed communication interfaces such as 5 Gbps Ethernet, PCIe, CAN-XL, and 10BASE-T1S Ethernet, providing flexibility and performance for various automotive applications.
* '''Enhanced Security''': Compliant with ISO 21434, the TC4x includes advanced cybersecurity modules and supports safe, over-the-air (SOTA) updates with zero downtime.
* '''Memory and Storage''': Features up to 25 MB of on-chip flash memory, allowing for complex software applications and data storage.
* '''Real-Time Control''': Advanced timers and ADCs (Analog-to-Digital Converters) improve control loops for electric motors and power conversion tasks.

== Architecture ==
[[File:Infineon TC4x Architecture.png|thumb|Infineon TC4x architecture|494x494px]]

=== System Architecture ===

=== TC 1.8P Processor Core (CPU0 ... CPU5) ===

=== Parallel Processing Unit (PPU) ===
The PPU is an implementation of the '''DesignWare ARC EV71 Processor'''. The length of the vector registers is flexible and depends on the version. Commercially, 128 or 256 bit vector registers are available. In a pre-series stepping even 512 bit was used.

See [[Infineon AURIX TC4x Parallel Processing Unit (PPU)]]

== Applications ==
* eMobility
* ADAS
* Automotive E/E architectures
* Affordable artificial intelligence (AI) applications

== emmtrix Tools for AURIX™ TC4x ==
emmtrix offers several tools for the Infineon AURIX™ TC4x architecture:

* [https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer] for vectorizing C code for the Infineon PPU. emmtrix was working together with Infineon already during develop of the TC4x architecture for supporting the PPU and received one of the first series A test boards.
* [https://www.emmtrix.com/tools/emmtrix-performance-estimatorator emmtrix Performance Estimator] for estimating the performance of C code written for the Tricore™ CPUs.

[[File:Infineon Board.png|thumb|Infineon Development Board (AURIX™ TC4x Communication Board)]]

=== emmtrix Code Vectorizer ===
[https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer (eCV)] simplifies programming the Parallel Processing Unit (PPU) on Infineon’s '''AURIX™ TC4x microcontrollers''', enabling significant acceleration of data-parallel applications like sensor fusion or AI inference. By leveraging the PPU, these tasks can be accelerated by factors >10, unlocking the full potential of hardware capabilities.

eCV automates the vectorization process, transforming sequential C code into optimized vectorized code tailored to the '''AURIX™ TC4x architecture'''. This includes efficient handling of memory layouts and advanced loop transformations. Developers can simulate and test functionality even without access to target hardware, reducing development time and effort.

With support for '''Simulink® models, ONNX-based AI workflows,''' and detailed performance insights through integrated simulators, eCV minimizes the need for manual optimization while maximizing hardware performance.[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.]]

=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / [[Infineon AURIX TC3xx|TC3xx]]/ TC4x microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

== See Also ==

* [[Infineon AURIX TC4x Parallel Processing Unit (PPU)]]
* [[Infineon AURIX TC3xx]]
* [[TriCore Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc4x/

[[Category:Supported Architectures]]

Infineon AURIX TC3xx

2025-04-08T08:01:46Z

Mira.steinmetz:

[[File:AURIX TC399 LFBGA-516 plain.jpg|thumb|Infineon AURIX™ TC3xx second-generation microcontroller (TC399 BGA package). The AURIX™ TC3xx family integrates multiple TriCore™ CPUs and on-chip safety/security modules for automotive applications.|alt=TC399 BGA package]]
The '''Infineon AURIX™ TC3xx''' (Automotive Realtime Integrated neXt-generation architecture) is a family of 32-bit automotive microcontrollers introduced as the second generation of Infineon’s AURIX™ platform. Launched in 2016 as a successor to the earlier [[Infineon AURIX TC2xx|AURIX™ TC2xx series]], the TC3xx devices emphasize high performance, functional safety, and embedded security for advanced automotive and industrial applications. AURIX™ TC3xx microcontrollers feature a hexa-core [[TriCore Instruction Set Architecture|''TriCore'' processor architecture]] with enhanced safety measures, making them well-suited for demanding tasks such as autonomous driving domain controllers, powertrain control, and sensor data fusion in advanced driver-assistance systems (ADAS). The combination of multiple CPU cores, extensive on-chip memory, and a rich peripheral set allows TC3xx chips to deliver real-time responsiveness and reliability in safety-critical environments while meeting stringent automotive standards (such as ISO 26262 for functional safety).<ref name="ref1951907555">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX™ https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref><ref name="ref1428109010">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref1948477695">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
==Applications==
AURIX™ TC3xx microcontrollers are used in a variety of safety-critical and high-performance applications across the automotive and industrial sectors. Key application domains include:
*'''Automotive Systems:''' The TC3xx family was primarily designed for automotive use and finds broad application in vehicles’ electronic control units (ECUs). Notably, it is used in ''powertrain and drivetrain control'' (engine management, transmission control, hybrid/electric vehicle inverter control, battery management) where its real-time processing and resilience support precise actuator control. It is also deployed in ''chassis and safety systems'' such as anti-lock braking systems (ABS), electronic stability control, airbag controllers, and electric power steering, leveraging its redundancy and fast response for fail-safe operation. With the growth of ADAS and autonomous driving, AURIX™ TC3xx devices serve as domain controllers for ''ADAS sensor fusion'', handling data from radar, LiDAR, camera, and ultrasonic sensors and performing environment modeling and decision-making algorithms. Their combination of multiple cores and a built-in radar signal processing sub-system makes them an attractive choice for tasks like front radar processing, sensor fusion hubs, and ''autonomous driving domain controllers'' that must meet ASIL-D safety levels.<ref name="ref14281090102">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
*'''Industrial Automation and Robotics:''' Infineon has also positioned the AURIX™ family for use in industrial applications that demand high reliability. The TC3xx MCUs, with their hardware self-test mechanisms and safety documentation, can be found in ''industrial motor drives, robotics controllers, and PLCs (programmable logic controllers)'', where they help achieve functional safety certifications up to SIL-3 (according to IEC 61508). The powerful TriCore™ cores and rich peripheral set enable complex motor control algorithms (e.g., field-oriented control for servo motors) and real-time sensor processing in factory automation. Additionally, the support for automotive-grade networking (CAN/CAN-FD, Ethernet) and timing peripherals makes them suitable for synchronous control in robotics and machinery. Infineon’s provision of AUTOSAR-compatible software for AURIX™ has even facilitated its use in non-automotive settings such as medical devices and elevator controllers, where proven safety and security are required.<ref name="ref496771205">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref>
*'''Aerospace and Defense:''' The high fault-tolerance and deterministic performance of the AURIX™ TC3xx architecture also attract interest for aerospace and other mission-critical uses. In avionics systems or autonomous drones, for instance, the lockstep core configuration and robust error checking of AURIX™ can provide an added layer of reliability for flight control computers or navigation systems. While primarily an automotive chip, its ability to operate in harsh conditions (−40°C to 150°C range) and to detect internal failures in real-time makes it viable for certain aerospace electronic systems. Some defense and aerospace projects leverage COTS (commercial off-the-shelf) automotive components like AURIX™ for applications such as unmanned vehicle control and high-reliability communication links, given its safety pedigree. (In these domains, additional analysis and possibly radiation testing would be performed if the devices are used in high-altitude or space environments.)
== Architecture Overview ==
[[File:Infineon TC3xx Architecture.webp|545x545px|thumb|alt=TC3xx Architecture Overview|TC3xx Architecture Overview]]
=== Processor Cores and Architecture===
The AURIX™ TC3xx family implements Infineon’s TriCore™ architecture, which uniquely combines aspects of RISC microcontrollers, DSP (digital signal processor) capabilities, and conventional microprocessor features into a single core design. Each TC3xx device can include up to six independent TriCore™ 32-bit CPU cores (TriCore™ version 1.6.2), all capable of running at up to 300 MHz clock frequency. Four of these cores can operate in dual-core lockstep pairs (with one core acting as a redundant checker for its partner) to provide fault detection for safety-critical functions. The TriCore™ cores use a superscalar Harvard architecture with 32-bit instruction words (and support for mixed 16/32-bit instruction encoding for code density). Each core includes a dedicated Floating Point Unit (FPU) for single-precision arithmetic and supports DSP-oriented instructions (e.g. single-cycle 16×16 MAC operations, SIMD for 16-bit/8-bit data) to accelerate signal processing tasks. For fast real-time performance, the architecture offers low interrupt latency (with automatic context save on-chip) and features like zero-overhead loops and a programmable peripheral timer unit for scheduling tasks. In total, a high-end TC3xx (such as the TC39x) provides six 300 MHz cores plus four checker cores, yielding a theoretical processing throughput of up to ~2400 DMIPS (Dhrystone MIPS) when all cores are utilized. This represents roughly a threefold increase in computational power over the previous AURIX™ generation (which achieved ~740 DMIPS with three cores).<ref name="ref19484776952">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref><ref name="ref2022357806">UDE Debug, Trace and Test solutions for Infineon TriCore™ AURIX™ TC32, TC33, TC35, TC36, TC37, TC38, TC39, TC3x Microcontrollers https://www.pls-mc.com/products/infineon-tricore-aurix-tc32-tc33-tc35-tc36-tc37-tc38-tc39-microcontrollers/</ref><ref name="ref14281090103">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref>
===Memory Subsystem and Cache===
AURIX™ TC3xx microcontrollers integrate a large on-chip memory system to meet real-time and safety requirements. Program flash memory sizes range up to 16 MB on the largest models, with over 6 MB of on-chip SRAM available for data and scratchpad usage. Each TriCore™ CPU has its own tightly-coupled local memories as well as caches: for example, each core includes a 32 KB instruction cache and a 16 KB data cache. In addition, every core has separate local RAM blocks (Harvard architecture) for instructions and data (often termed PSPR and DSPR – Program Scratch-Pad RAM and Data Scratch-Pad RAM) that allow deterministic access for time-critical routines. Shared global memory is provided via a Local Memory Unit (LMU) which can be up to several hundred kilobytes (for instance, 768 KB in the TC39x) accessible by all cores. The memory system is connected by a high-bandwidth internal bus fabric (the SRI crossbar and peripheral buses) that arbitrates access between cores, DMA engines, and peripherals. This architecture ensures that each core can quickly fetch instructions and data either from its local cache/RAM or the central memory, enabling efficient parallel processing. Memory protection hardware is also built-in to isolate tasks of different criticality, an important feature for safety and security.<ref name="ref19484776952" /><ref name="ref5727814512">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
===Peripherals and Interfaces===
One of the strengths of the AURIX™ TC3xx architecture is its extensive set of on-chip peripherals and interface controllers, designed to handle the complex networking and I/O needs of modern vehicles and industrial systems. Key peripheral features and interfaces include:<ref name="ref19484776952" /><ref name="ref2022357806" /><ref name="ref14281090103" /><ref name="ref3635926">AURIX™ Training System Architecture https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_System_Architecture-Training-v01_00-EN.pdf?fileId=5546d46272e49d2a0172eb476d56739e</ref>

* '''Networking Interfaces:''' Multiple CAN FD controllers (supporting up to 12 CAN-FD channels in high-end variants) for in-vehicle networking, with legacy CAN and LIN interfaces (up to 24 LIN channels) for lower-speed device communication. Many TC3xx devices also integrate up to two FlexRay controllers for time-triggered automotive networks (maintaining compatibility with earlier automotive communication standards). For high-bandwidth data, a Gigabit Ethernet MAC is included, enabling uses like automotive Ethernet (e.g., audio-video bridging and IP-based connectivity).
* '''Analog and Timers:''' A suite of analog peripherals including multiple ADC units for sensor interfacing and motor control, and DACs in some models. Sophisticated timer units are on-chip, notably the Generic Timer Module (GTM) and Capture/Compare Units (CCU6), which can generate complex PWM waveforms and handle events for engine control, power inverters, or robotics with minimal CPU intervention. These timers enable precise control of actuators (e.g. fuel injection timing, electric motor commutation) in real time.
*'''Serial Interfaces:''' SPI, I²C, UART/LIN and other serial interfaces for connecting to external sensors, actuator controllers, and memory. The controllers often support multiple instances (several SPI channels, etc.) to accommodate numerous devices. AURIX™ TC3xx also provides an external bus interface (EBU) for parallel memory or FPGA connectivity, and an SD/MMC interface (eMMC) to connect external flash memory for data logging or over-the-air update storage.
*'''Dedicated Processing Units:''' Some AURIX™ TC3xx models include special accelerators, such as a hardware Fast Fourier Transform unit (HW-FFT) and up to two Signal Processing Units (SPUs) optimized for radar signal processing. These enable the microcontroller to handle radar front-end data or other intensive DSP tasks (like Fourier transforms for radar or audio signals) on-chip, which is crucial for advanced driver assistance sensors. There is also a ''Security Module'' (covered in a later section) and a Safety Management Unit that supervise system integrity.
*'''Other On-chip Modules:''' Watchdog timers, error-correction coders for memories (ECC on flash and RAM for reliability), a programmable interrupt system, multiple DMA channels (up to 128 DMA channels) for efficient data movement, and debug interfaces (JTAG and a 2/3-pin DAP) for development. The on-chip debug system supports tracing of program execution (via a built-in Emulation Memory, MCDS) to aid in complex multicore software development.

Overall, the AURIX™TC3xx provides a highly integrated SoC-like platform, allowing a single chip to manage tasks ranging from powertrain control and chassis control to infotainment gateways. This high level of integration reduces the need for separate companion chips and helps to lower system complexity and cost.
===Performance and Benchmarking===
Fabricated in a 40 nm embedded flash process<ref name="ref2022357806" />, AURIX™ TC3xx processors achieve significant performance gains over prior generations while maintaining automotive-grade power efficiency. With six 32-bit cores at 300 MHz (four of them paired in lockstep), a flagship TC3xx device (e.g., TC39x) can deliver up to approximately 2,400 DMIPS of aggregate computing throughput<ref name="ref2022357806" />. In terms of per-core performance, the TriCore™ architecture yields around 1.3–2.0 DMIPS/MHz depending on the instruction mix, meaning each 300 MHz core can approach ~400–600 DMIPS in optimized scenarios<ref name="ref14281090103" /><ref name="ref1222155140">Infineon AURIX™ - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. This is on par with or exceeding many contemporary 32-bit automotive MCUs. The integrated DSP extensions and optional accelerators (like the FFT unit) also enable high-speed signal processing, with Infineon citing up to ~1.8 GFLOPS of DSP throughput for certain operations<ref name="ref1222155140" />.

Real-world performance improvements of the TC3xx over its predecessor are notable: for example, compared to the first-generation AURIX™ (which offered up to 740 DMIPS), the TC3xx’s expanded core count and clock speed provide roughly three times the computational power on the same type of workload<ref name="ref14281090103" />. This extra headroom allows more functions (such as running multiple control algorithms or sensor fusion tasks in parallel) to be consolidated onto one microcontroller without compromising real-time deadlines<ref name="ref14281090103" />. Despite the increase in speed and core count, the TC3xx family was designed with power and thermal constraints in mind, achieving these gains within similar power consumption envelopes as the previous generation by leveraging the smaller 40 nm process and power-saving features like clock gating<ref name="ref5727814512" />. The deterministic real-time performance (with features like lockstep and tightly-coupled memory) makes the AURIX™ TC3xx suitable for the most demanding automotive applications, where consistent low latency and high throughput are required simultaneously.

== On-Chip System Connectivity and Bridges ==
[[File:TC3xx On-Chip System Connectivity.png|thumb|The TC3xx has two '''SRI Domains''' (SRI0 and SRI1). CPU0 to CPU3 are connected to SRI0, CPU4/5 are connected to SRI1.|alt=TC3xx On-Chip System Connectivity|423x423px]]
The AURIX™ TC3xx Platform has three independent on-chip connectivity resources:

* '''System Resource Interconnect Fabric (SRI Fabric)''' connects the TriCore™ CPUs, the DMA module, and other high bandwidth requestors to high bandwidth memories and other resources for instruction fetches and data accesses. A key component of the fabric is the SRI crossbar, which connects all the agents in one SRI domain. The SRI crossbar carries the transactions between the SRI Masters and SRI Slaves of the domain. The SRI crossbar supports parallel transactions between different SRI Master and SRI Slave agents. In addition to the parallelism of concurrent requests, it also supports pipelined requests from an SRI Master to a SRI Slave.
* '''System Peripheral Bus (SPB)''' connects the TriCore™ CPUs, the DMA module, and other SPB masters to the medium and low bandwidth peripherals. SPB masters do not directly connect to the SRI Fabric, and will access SRI attached resources via a SFI_F2S Bridge.
* '''Back Bone Bus (BBB)''' connects the TriCore™ CPUs, the DMA module, and SPB masters with ADAS resources. SRI Masters do not directly connect to the BBB, but access BBB attached resources via a SFI_S2F Bridge. SPB masters also do not directly connect to the BBB, but access BBB attached resources via bridging over the SRI Fabric.

=== CPU Resource Access Times ===
These tables describe the CPU access times to various resources in CPU clock cycles for the AURIX™ TC3xx Platform. In the case of load or fetch accesses, the access times are the minimum number of CPU stall cycles to complete the access. If there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

For write access, the access times are the maximum for a sequence of such access (non-conflicting). In many cases for a singleton access, or a short sequence, write buffering reduces the stall effect seen by a CPU, sometimes to 0. However, as with loads and fetches, if there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

==== Access latency for global resources ====
{| class="wikitable"
|+
! CPU Access Type !! CPU stall cycles
!Notes
|-
| Data read from System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
| rowspan="2" |The final number of stall cycles will depend on the real number of WS generated by the target resource.
|-
| Data write to System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC39x, TC37xED) || <math>9 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
| rowspan="2" |When SFI_S2F is connected to XBar2 (TC39x and TC37xED) there is an additional latency due to access going through an S2S.
|-
| Data write to Back Bone Bus (BBB) (TC39x, TC37xED) || <math>5 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC35x, TC33xED) || <math>6 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
|
|-
| Data write to Back Bone Bus (BBB) (TC35x, TC33xED) || <math>3 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|
|}


* '''Module Wait State''': The number of wait states for read and for write accesses is >= 1 and depends on the accessed module and its configuration.


==== CPU Accesses: Stall cycles for local and SRI resources ====
{| class="wikitable"
|+
! CPU Access Type !! Local CPU !! Local SRI !! Remote SRI Domain
|-
| Data read from DSPR || 0 || 7 || 10
|-
| Data write to DSPR || 0 || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from DSPR || See local SRI column || 7 || 10
|-
| Data read from DLMU || 0 || 7 || 10
|-
| Data write to DLMU || 2 || 5, {{rev|3|with Pipelining}}|| 5, 4
|-
| Instruction fetch from DLMU || See local SRI column || 7 || 10
|-
| Data read from PSPR || See local SRI column || 7 || 10
|-
| Data write to PSPR || See local SRI column || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from PSPR || 0 || 7 || 10
|-
| Data read from PFlash || 5 + PWS || 10 + PWS || 13 + PWS
|-
| Instruction fetch from PFlash (buffer miss) || 2 + PWS || 9 + PWS || 12 + PWS
|-
| Instruction fetch from PFlash (buffer hit) || 3 || 6 || 9
|-
| Data read from LMU || n.a. || 7 || 10
|-
| Data write to LMU || n.a. || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from LMU || n.a. || 7 || 10
|-
| Data read from DFlash || n.a. || 5 + 3*(3 + DCWS) || 8 + 3*(3 + DCWS)
|-
| Data read access from EMEM (TC39x, TC37xED) || n.a. || n.a. || 14, {{rev|15|fBBB < fSRI}}
|-
| Data write access to EMEM (TC39x, TC37xED) || n.a. || n.a. || 9
|-
| Data read access from EMEM (TC35x, TC33xED) || n.a. || 11, {{rev|12|fBBB < fSRI}}|| n.a.
|-
| Data write access to EMEM (TC35x, TC33xED) || n.a. || 9 || n.a.
|-
| Data read access from DAM || n.a. || 10 || 13
|-
| Data write access to DAM || n.a. || 7 || 7
|}

* '''Remote SRI Domain''': Only applies to products with SRI extenders. Additional latency due to access going through an S2S
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''DCWS''': Configured DFlash Corrected Wait States (Includes cycles for DFlash access cycles and ECC correction latency)

== CPU Subsystem ==
[[File:TC3xx Processor Core, Local Memory and Connectivity.png|alt=TC3xx Processor Core, Local Memory and Connectivity|thumb|Processor Core, Local Memory and Connectivity]]The Infineon AURIX™ TC3xx features up to 6 processor cores (CPU0 ... CPU5) implementing the [[TriCore Instruction Set Architecture|TC1.6.2 instruction set architecture]]. The following section focuses on the microarchitectural details of the CPU subsystem. For more information about the ISA, please take a look at the [[TriCore Instruction Set Architecture]].

The processor core connects to the following memories and bus interfaces (where implemented):
*Program Scratch-Pad SRAM (PSPR)
*Data Scratch-Pad SRAM (DSPR)
*Program Cache (PCache)
*Data Cache (DCache)
*Local Memory Unit (DLMU)
*Local Pflash bank (LPB)
*SRI slave interface (x2)
*SRI master Interface
*SPB master interface

=== TC1.6.2P Implementation Features ===
*Most instructions executed in 1 cycle
*Branch instructions in 1, 2 or 3 cycles (using dynamic branch prediction)
*Wide memory interface for fast context switch
* Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
*Six memory protection register sets
*Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
*Third pipeline for loop instruction only (zero overhead loop)
*Single precision Floating Point Unit (IEEE-754 Compatible)
*Dedicated Integer divide unit
*18 data memory protection ranges, 10 code memory protection ranges arranged in 6 sets

=== Superscalar Architecture ===
The processor core within the AURIX™ TC3xx family, specifically the TC1.6.2P implementation, employs a superscalar architecture characterized by three parallel pipelines: the Integer Pipeline, the Load/Store Pipeline, and the Loop Pipeline. Superscalar execution is a form of instruction-level parallelism that enables the processor to issue and execute multiple instructions during a single clock cycle. The TriCore™ TC3xx core's superscalar architecture allows it to issue and execute multiple instructions in parallel. Specifically, it can issue up to two instructions simultaneously to the Integer and Load/Store pipelines. However, there are certain constraints on this dual issuing capability. For example, back-to-back data arithmetic instructions can only be issued in separate cycles, and a load/store instruction can be issued either on its own or paired with a data arithmetic instruction, provided the load/store instruction is the second in the pair. Under ideal conditions, with careful instruction scheduling, this dual-issue capability can lead to a throughput of close to 0.5 clock cycles per instruction, effectively executing two instructions per cycle.

=== Pipeline Stages ===
The execution of instructions within the TriCore™ TC3xx core is managed through a pipeline consisting of several stages. In one document it is mentioned that the pipeline consists of 6 stages <ref name="ref3635926" />, but the exact stages remain unclear. From the architecture the following stages can be inferred:

* '''Fetch Stage''': The initial stage in the pipeline is the Fetch stage, where instructions are retrieved from memory. This task is handled by the Instruction Fetch Unit (IFU), which is responsible for fetching instructions from the memory system. To improve efficiency, the IFU employs a pre-fetching mechanism, anticipating the instructions that will be needed and bringing them into the processor before they are actually required. Instructions are fetched through a 64-bit wide Program Memory Interface (PMI), allowing for the retrieval of a significant amount of instruction data in each cycle. The fetched instructions are then placed into an issue FIFO, a buffer capable of holding up to six instructions. This buffer plays a crucial role in managing the flow of instructions to the subsequent execution pipelines. The 64-bit fetch width and the instruction buffer are indicative of a design that aims to ensure a continuous supply of instructions to the pipelines, preventing them from being starved of work. A wider fetch path allows for more instruction bits to be obtained from memory in each clock cycle, while the buffer helps to mitigate temporary delays in instruction fetching.
* '''Execution Unit''': The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop Pipeline. All three pipelines operate in parallel and are capable of executing instructions simultaneously. Each pipline has its own decode stage and two execute stages. Furthermore, the TC3xx features a Floating Point Unit (FPU). It is not clear whether the FPU is part of the execution unit or a separate unit. It is assumed that the FPU also has its own decode stage and an unknown number of execute stages
** '''Decode Stage''': Following the Fetch stage, the instruction are issued to one of the pipelines. In the decode stage of each pipeline, the instruction is examined and translated to determine the specific operation it represents and to identify the operands it will operate on. It is assumed that operands are read from the register file during the decode stage.
** '''Execute Stage''': The Execute stage is where the actual operation specified by the instruction is carried out. Pipeline hazards (stalls) are minimised by the use of forwarding paths between pipeline stages allowing the results of one instruction to be used by a following instruction as soon as the result becomes available.
** '''Writeback Stage''': The final stage in the pipeline is the Writeback stage. In this stage, the results produced by the executed instruction are written back to the processor's register file, making them available for subsequent instructions. It is unclear whether the writeback stage is part of the (two) execution stages or a separate stage.

=== Execution Pipelines ===
The TriCore™ TC3xx core leverages four parallel pipelines to enhance its performance. Each pipeline is designed to handle a specific class of instructions:

* '''Integer Pipeline:''' This pipeline is responsible for executing integer arithmetic and logical instructions, including data-conditional jump instructions, bit manipulation operations, as well as division and multiply-accumulate (MAC) instructions.
* '''Load/Store Pipeline:''' The primary function of this pipeline is to manage memory access operations, including loading data from memory and storing data to memory. It also handles address arithmetic, unconditional jump instructions, procedure call instructions, context-switching operations, and control flow related to context save areas (CSAs).
* '''Loop Pipeline:''' This is a specialized pipeline designed to facilitate zero-overhead loops, a technique that significantly improves the performance of iterative code sections. Its design aims to eliminate or minimize the overhead typically associated with loop control, such as incrementing counters and checking loop conditions. Some documentation suggests that the loop pipeline comes along with a "Loop Cache". This dedicated cache would likely be used to store instructions belonging to the loop, enabling very fast access and execution for repeated iterations.
* '''Floating Point Unit (FPU):''' The FPU is responsible for executing floating-point arithmetic operations

=== Store Buffers ===
The TriCore™ TC3xx core include '''Store Buffers''' to decouple memory write operations from CPU instruction execution. All stores from the Load/Store Pipeline are placed in the store buffer prior to being written to local memory or transferred via the bus system. Write data is taken from the store buffers and written to memory when the target memory or bus interface becomes available. In normal operation the CPU will prioritise memory load operations over store operations in order to improve performance unless the store buffer is full or the order of load and store operations must be preserved (e.g. peripheral space access). The store buffer can hold the data for up to 6 stores operations. To improve performance the store buffer will merge consecutive byte, half-word, and word writes of the same location to reduce the number of memory accesses required.

=== Instruction Timing ===

==Functional Safety and Security Features==
===Hardware Security Module and Encryption===
One of the defining features of the AURIX™ TC3xx family is its robust hardware-based security subsystem, implemented to protect against cyber threats and unauthorized manipulation of vehicle systems. Each TC3xx MCU includes a dedicated ''Hardware Security Module'' (HSM), which is essentially an on-chip co-processor with its own CPU and cryptographic engine designed to handle secure operations. In the second-generation AURIX™ (TC3xx), the HSM was upgraded with support for asymmetric cryptography (e.g., RSA, ECC algorithms) in hardware, providing significantly faster public-key encryption and authentication capabilities than pure software implementations. This HSM supports '''EVITA Full''' (the highest level of the EU’s EVITA automotive security requirements), meaning it can perform secure boot, message authentication, and encryption at a level suitable for protecting critical in-vehicle communications. For example, the HSM can encrypt and authenticate CAN/Ethernet messages to prevent spoofing or tampering on the vehicle network, and it can manage cryptographic keys securely isolated from the main application cores.<ref name="ref14281090104">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref2022357806" />

The security module enables features like '''secure boot''', where the AURIX™ will only execute firmware that is digitally signed by the vehicle manufacturer, thereby preventing unauthorized or malicious code. It also facilitates ''over-the-air (OTA) updates'' in a secure manner: the TC3xx HSM can verify and decrypt update packages received via telematics, allowing firmware upgrades while protecting against attackers attempting to hijack the software. In addition, the HSM includes a true random number generator and supports protocols for immobilizer and theft protection systems. Infineon’s implementation essentially treats the HSM as an “embedded smart card” inside the microcontroller. This approach, building on Infineon’s expertise in chip card security, helps to safeguard sensitive assets like cryptographic keys and to perform secure operations (encryption, decryption, authentication) in hardware, making attacks significantly more difficult. The strong cybersecurity provisions of the AURIX™ TC3xx have made it a preferred choice for vehicle gateway ECUs and central body controllers, which are points of entry for connected car communications and thus high-value targets for hackers. By incorporating the HSM, automotive OEMs can implement advanced security features such as encrypted onboard communication (to thwart bus tampering) and secure diagnostics, ensuring the vehicle’s electronic data is protected against cyber threats even as cars become more connected.<ref name="ref14281090104" /><ref name="ref5727814513">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref><ref name="ref19484776953">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
=== Functional Safety and Fault Tolerance===
Beyond cybersecurity, the AURIX™ TC3xx architecture is built with extensive ''functional safety'' features to meet the highest safety integrity levels in automotive systems. The multi-core design supports ''lockstep operation'', where redundant checker cores run in parallel with main cores and continuously compare results cycle-by-cycle. In TC3xx devices, up to four of the six TriCore™ CPUs have such lockstep partner cores, allowing the microcontroller to detect any single-point CPU failure instantly (if a discrepancy arises between the core and its checker, a fault is signaled). A ''Safety Management Unit (SMU)'' is integrated on-chip to monitor various fault conditions throughout the device – it aggregates error signals from the lockstep cores, memory ECC monitors, clock/watchdog monitors, and peripheral self-tests, and can initiate safe-state actions (like resetting the chip or signaling an error pin to an external supervisor) if a critical fault is detected. The AURIX™ safety concept also includes a distributed Memory Protection Unit (MPU) arrangement, with multiple memory protection contexts that prevent errant or malicious code from writing to wrong memory areas. This helps contain faults and eases the integration of software with mixed criticality (Infineon allows partitioning software components of different ASIL levels on the same MCU while keeping them isolated).<ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref19519075552">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX™ https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref>

Crucially, the TC3xx family was developed according to ISO 26262 processes and can achieve '''ASIL-D''' (Automotive Safety Integrity Level D), the highest grade for automotive functional safety. Compared to a traditional dual-core lockstep approach, the AURIX’s™ multi-core safety architecture allowed Infineon to reduce certain safety development overheads (earlier Infineon data suggested up to 30% reduction in safety software workload) by providing built-in safety mechanisms and diagnostics. Infineon supplies a comprehensive safety manual and diagnostic libraries for the AURIX™, helping engineers utilize features like CPU self-tests, RAM tests, and CRC checks to comply with safety standards. In addition to automotive standards, the AURIX™ TC3xx has also been qualified for '''industrial safety''': in 2023, Infineon announced support for IEC 61508 metrics, enabling designs with AURIX™ to reach SIL-2 and SIL-3 safety integrity levels for industrial applications. This cross-industry safety compliance is facilitated by the MCU’s redundant design and detailed failure mode documentation (FMEDA) provided by Infineon. In summary, the AURIX™ TC3xx integrates both proactive safety (fault prevention via lockstep, monitoring and protection) and reactive safety (fault detection and safe shutdown), making it a dependable component for systems that cannot afford unintended behavior, whether in cars, factories, or aerospace. <ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref4967712052">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref><ref name="ref196858272">MCUs support industrial functional safety - Electronic Products https://www.electronicproducts.com/mcus-support-industrial-functional-safety/</ref>
== Platform Devices ==
The following table shows a feature overview of the AURIX™ TC3xx Platform family focusing on memory and number of cores.
{| class="wikitable"
!
!Feature
!TC33x
!TC33xEXT
!TC35x
!TC36x
!TC37x
!TC37xEXT
!TC38x
!TC39x
|-
| rowspan="2" |CPUs
|Cores / Checker Cores
|1 / 1
|2 / 1
|3 / 2
|2 / 2
|3 / 2
|3 / 3
|4 / 2
|6 / 4
|-
|Max. Freq.
| colspan="8" |300 MHz
|-
| rowspan="2" |Cache per CPU
|Program [KB]
| colspan="8" |32
|-
|Data [KB]
| colspan="8" |16
|-
| rowspan="3" |SRAM per CPU
|PSPR [KB]
|8
|{{rev|32|CPU0}}
{{rev|64|other}}
|64
|32
|64
|64
|64
|64
|-
|DSPR [KB]
|192
|{{rev|192|CPU0}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|192
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|-
|DLMU [KB]
|8
|{{rev|8|CPU0}}
{{rev|64|other}}
|64
|64
|64
|64
|64
|64
|-
| rowspan="2" |SRAM global
|LMU [KB]
| -
| -
|512
| -
| -
| -
|128
|768
|-
|DAM [KB]
| -
| -
|32
| -
|64
|64
|128
|128
|-
| rowspan="3" |Extension Memory (EMEM)
|TCM [MB]
| -
|1
|2
| -
| -
|2
| -
|2
|-
|XCM [MB]
| -
| -
| -
| -
| -
|1
| -
|2
|-
|XTM [KB]
| -
|16
|16
| -
| -
|16
| -
|16
|-
| rowspan="2" |Program Flash
|Size [MB]
|2
|4
|4
|4
|6
|10
|10
|16
|-
|Banks [MB]
|1 x 2
|2 x 2
|2 x 2
|2 x 2
|2 x 3
|3 x 3, 1 x 1
|3 x 3, 1 x 1
|5 x 3, 1 x 1
|-
| rowspan="2" |Data Flash
|DF0 Size (single-ended) [KB]
|128
|128
|128
|128
|256
|512
|512
|1024
|-
|DF1 Size (single-ended) [KB]
|128
|128
|128
|128
|128
|128
|128
|128
|-
| rowspan="3" |DMA
|Channels
|64
|64
|64
|64
|128
|128
|128
|128
|-
|Move Engines
|2
|2
|2
|2
|2
|2
|2
|2
|-
|Resource Partitions
|4
|4
|4
|4
|4
|4
|4
|4
|}

== Compilers ==
The AURIX™ TC3xx family is a series of high-performance microcontrollers widely used in automotive and industrial applications. Compilers for the AURIX™ TC3xx are crucial for developers aiming to optimize performance, reliability, and safety in their applications. One significant aspect of the compiler landscape for AURIX™ TC3xx is the limited direct support from mainline open-source compilers such as GCC or LLVM/Clang. The primary reason for this is the stringent requirements for functional safety in automotive and industrial applications, which demand specialized features and compliance with safety standards that are often not met by general-purpose open-source compilers.

=== Commercial Compilers ===

# '''Tasking''': Tasking compilers are renowned for their robust support for automotive applications, offering advanced debugging capabilities and optimization techniques tailored for the AURIX™ architecture. They provide extensive code optimization, comprehensive debugging tools, and strong support for safety standards such as ISO 26262, making them ideal for developing high-performance, reliable, and safe applications.
# '''HighTec''': The HighTec compiler is a popular choice, known for its Eclipse-based development environment and strong multicore support. HighTec provides both GCC and LLVM-based ports of open-source compilers tailored specifically for the AURIX™ TC3xx family. These compilers offer efficient parallel execution, advanced code analysis, and an integrated development environment, ensuring robust performance and compliance with safety standards.
# '''Green Hills Software''': Green Hills Software provides a highly optimized toolchain aimed at safety-critical applications, focusing on high performance and strict compliance with automotive standards. Their compiler offers superior optimization, extensive safety features, and a proprietary IDE with specialized tools for automotive development, ensuring developers can meet the stringent demands of functional safety.

=== GCC for AURIX™ ===

While mainline GCC does not directly support the AURIX™ TC3xx family, there is an unofficial GCC version available for AURIX™. Due to the GNU General Public License (GPL), the source code from HighTec was retrieved and, along with binary versions, published on GitHub:

*GCC 4.9.4/Binutils 2.20/Newlib 1.18 for Tricore™ AURIX™ [[https://github.com/volumit/package_494 Source]] [[https://github.com/volumit/tricore_gcc494_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc494_linux_bins Prebuild Linux Binaries]]
*GCC 9.4.0/Binutils 2.20/Newlib 1.18 for Tricore™ AURIX™ [[https://github.com/volumit/package_940 Source]] [[https://github.com/volumit/tricore_gcc940_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc940_linux_bins Prebuild Linux Binaries]]
*GDB 10.0.50 for Tricore™ AURIX™ [[https://github.com/volumit/gdb-tricore Source]]
==emmtrix Tools for AURIX™ TC3xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX™ TC3xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

==See Also==

*[[Infineon AURIX TC4x|Infineon AURIX™ TC4x]]
*[[Infineon AURIX TC2xx|Infineon AURIX™ TC2xx]]
*[[TriCore Instruction Set Architecture]]

==External Links==

*https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/
*[https://documentation.infineon.com/aurixtc3xx/docs/qmd1702366622648 AURIX™ TC3xx user manuals]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d3605221d96 AURIX™ TC3xx User Manual Part-1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d35f8541d94 AURIX™ TC3xx User Manual Part-2]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd AURIX™ TC3xx Architecture vol 1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 AURIX™ TC3xx Architecture vol 2]

== References ==
<references />
[[Category:Supported Architectures]]

{{#seo:
|title=Infineon AURIX TC3xx Family – Deep Dive
|description=This deep dive into Infineon's AURIX TC3xx family explores its multi-core TriCore architecture, real-time capabilities, safety and security features and tools
|image=File:AURIX_TC399_LFBGA-516_plain.jpg
|keywords=AURIX, Infineon, TC3xx, microcontroller, TriCore, automotive, ADAS, ISO 26262, functional safety, embedded security, ASIL-D, deep dive
}}

Infineon AURIX TC3xx

2025-04-08T07:53:31Z

Mira.steinmetz:

[[File:AURIX TC399 LFBGA-516 plain.jpg|thumb|Infineon AURIX™ TC3xx second-generation microcontroller (TC399 BGA package). The AURIX™ TC3xx family integrates multiple TriCore CPUs and on-chip safety/security modules for automotive applications.|alt=TC399 BGA package]]
The '''Infineon AURIX™ TC3xx''' (Automotive Realtime Integrated neXt-generation architecture) is a family of 32-bit automotive microcontrollers introduced as the second generation of Infineon’s AURIX™ platform. Launched in 2016 as a successor to the earlier [[Infineon AURIX TC2xx|AURIX™ TC2xx series]], the TC3xx devices emphasize high performance, functional safety, and embedded security for advanced automotive and industrial applications. AURIX™ TC3xx microcontrollers feature a hexa-core [[TriCore Instruction Set Architecture|''TriCore'' processor architecture]] with enhanced safety measures, making them well-suited for demanding tasks such as autonomous driving domain controllers, powertrain control, and sensor data fusion in advanced driver-assistance systems (ADAS). The combination of multiple CPU cores, extensive on-chip memory, and a rich peripheral set allows TC3xx chips to deliver real-time responsiveness and reliability in safety-critical environments while meeting stringent automotive standards (such as ISO 26262 for functional safety).<ref name="ref1951907555">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX™ https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref><ref name="ref1428109010">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref1948477695">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
==Applications==
AURIX™ TC3xx microcontrollers are used in a variety of safety-critical and high-performance applications across the automotive and industrial sectors. Key application domains include:
*'''Automotive Systems:''' The TC3xx family was primarily designed for automotive use and finds broad application in vehicles’ electronic control units (ECUs). Notably, it is used in ''powertrain and drivetrain control'' (engine management, transmission control, hybrid/electric vehicle inverter control, battery management) where its real-time processing and resilience support precise actuator control. It is also deployed in ''chassis and safety systems'' such as anti-lock braking systems (ABS), electronic stability control, airbag controllers, and electric power steering, leveraging its redundancy and fast response for fail-safe operation. With the growth of ADAS and autonomous driving, AURIX™ TC3xx devices serve as domain controllers for ''ADAS sensor fusion'', handling data from radar, LiDAR, camera, and ultrasonic sensors and performing environment modeling and decision-making algorithms. Their combination of multiple cores and a built-in radar signal processing sub-system makes them an attractive choice for tasks like front radar processing, sensor fusion hubs, and ''autonomous driving domain controllers'' that must meet ASIL-D safety levels.<ref name="ref14281090102">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
*'''Industrial Automation and Robotics:''' Infineon has also positioned the AURIX™ family for use in industrial applications that demand high reliability. The TC3xx MCUs, with their hardware self-test mechanisms and safety documentation, can be found in ''industrial motor drives, robotics controllers, and PLCs (programmable logic controllers)'', where they help achieve functional safety certifications up to SIL-3 (according to IEC 61508). The powerful TriCore cores and rich peripheral set enable complex motor control algorithms (e.g., field-oriented control for servo motors) and real-time sensor processing in factory automation. Additionally, the support for automotive-grade networking (CAN/CAN-FD, Ethernet) and timing peripherals makes them suitable for synchronous control in robotics and machinery. Infineon’s provision of AUTOSAR-compatible software for AURIX™ has even facilitated its use in non-automotive settings such as medical devices and elevator controllers, where proven safety and security are required.<ref name="ref496771205">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref>
*'''Aerospace and Defense:''' The high fault-tolerance and deterministic performance of the AURIX™ TC3xx architecture also attract interest for aerospace and other mission-critical uses. In avionics systems or autonomous drones, for instance, the lockstep core configuration and robust error checking of AURIX™ can provide an added layer of reliability for flight control computers or navigation systems. While primarily an automotive chip, its ability to operate in harsh conditions (−40°C to 150°C range) and to detect internal failures in real-time makes it viable for certain aerospace electronic systems. Some defense and aerospace projects leverage COTS (commercial off-the-shelf) automotive components like AURIX™ for applications such as unmanned vehicle control and high-reliability communication links, given its safety pedigree. (In these domains, additional analysis and possibly radiation testing would be performed if the devices are used in high-altitude or space environments.)
== Architecture Overview ==
[[File:Infineon TC3xx Architecture.webp|545x545px|thumb|alt=TC3xx Architecture Overview|TC3xx Architecture Overview]]
=== Processor Cores and Architecture===
The AURIX™ TC3xx family implements Infineon’s TriCore™ architecture, which uniquely combines aspects of RISC microcontrollers, DSP (digital signal processor) capabilities, and conventional microprocessor features into a single core design. Each TC3xx device can include up to six independent TriCore 32-bit CPU cores (TriCore version 1.6.2), all capable of running at up to 300 MHz clock frequency. Four of these cores can operate in dual-core lockstep pairs (with one core acting as a redundant checker for its partner) to provide fault detection for safety-critical functions. The TriCore cores use a superscalar Harvard architecture with 32-bit instruction words (and support for mixed 16/32-bit instruction encoding for code density). Each core includes a dedicated Floating Point Unit (FPU) for single-precision arithmetic and supports DSP-oriented instructions (e.g. single-cycle 16×16 MAC operations, SIMD for 16-bit/8-bit data) to accelerate signal processing tasks. For fast real-time performance, the architecture offers low interrupt latency (with automatic context save on-chip) and features like zero-overhead loops and a programmable peripheral timer unit for scheduling tasks. In total, a high-end TC3xx (such as the TC39x) provides six 300 MHz cores plus four checker cores, yielding a theoretical processing throughput of up to ~2400 DMIPS (Dhrystone MIPS) when all cores are utilized. This represents roughly a threefold increase in computational power over the previous AURIX™ generation (which achieved ~740 DMIPS with three cores).<ref name="ref19484776952">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref><ref name="ref2022357806">UDE Debug, Trace and Test solutions for Infineon TriCore™ AURIX™ TC32, TC33, TC35, TC36, TC37, TC38, TC39, TC3x Microcontrollers https://www.pls-mc.com/products/infineon-tricore-aurix-tc32-tc33-tc35-tc36-tc37-tc38-tc39-microcontrollers/</ref><ref name="ref14281090103">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref>
===Memory Subsystem and Cache===
AURIX™ TC3xx microcontrollers integrate a large on-chip memory system to meet real-time and safety requirements. Program flash memory sizes range up to 16 MB on the largest models, with over 6 MB of on-chip SRAM available for data and scratchpad usage. Each TriCore CPU has its own tightly-coupled local memories as well as caches: for example, each core includes a 32 KB instruction cache and a 16 KB data cache. In addition, every core has separate local RAM blocks (Harvard architecture) for instructions and data (often termed PSPR and DSPR – Program Scratch-Pad RAM and Data Scratch-Pad RAM) that allow deterministic access for time-critical routines. Shared global memory is provided via a Local Memory Unit (LMU) which can be up to several hundred kilobytes (for instance, 768 KB in the TC39x) accessible by all cores. The memory system is connected by a high-bandwidth internal bus fabric (the SRI crossbar and peripheral buses) that arbitrates access between cores, DMA engines, and peripherals. This architecture ensures that each core can quickly fetch instructions and data either from its local cache/RAM or the central memory, enabling efficient parallel processing. Memory protection hardware is also built-in to isolate tasks of different criticality, an important feature for safety and security.<ref name="ref19484776952" /><ref name="ref5727814512">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
===Peripherals and Interfaces===
One of the strengths of the AURIX™ TC3xx architecture is its extensive set of on-chip peripherals and interface controllers, designed to handle the complex networking and I/O needs of modern vehicles and industrial systems. Key peripheral features and interfaces include:<ref name="ref19484776952" /><ref name="ref2022357806" /><ref name="ref14281090103" /><ref name="ref3635926">AURIX™ Training System Architecture https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_System_Architecture-Training-v01_00-EN.pdf?fileId=5546d46272e49d2a0172eb476d56739e</ref>

* '''Networking Interfaces:''' Multiple CAN FD controllers (supporting up to 12 CAN-FD channels in high-end variants) for in-vehicle networking, with legacy CAN and LIN interfaces (up to 24 LIN channels) for lower-speed device communication. Many TC3xx devices also integrate up to two FlexRay controllers for time-triggered automotive networks (maintaining compatibility with earlier automotive communication standards). For high-bandwidth data, a Gigabit Ethernet MAC is included, enabling uses like automotive Ethernet (e.g., audio-video bridging and IP-based connectivity).
* '''Analog and Timers:''' A suite of analog peripherals including multiple ADC units for sensor interfacing and motor control, and DACs in some models. Sophisticated timer units are on-chip, notably the Generic Timer Module (GTM) and Capture/Compare Units (CCU6), which can generate complex PWM waveforms and handle events for engine control, power inverters, or robotics with minimal CPU intervention. These timers enable precise control of actuators (e.g. fuel injection timing, electric motor commutation) in real time.
*'''Serial Interfaces:''' SPI, I²C, UART/LIN and other serial interfaces for connecting to external sensors, actuator controllers, and memory. The controllers often support multiple instances (several SPI channels, etc.) to accommodate numerous devices. AURIX™ TC3xx also provides an external bus interface (EBU) for parallel memory or FPGA connectivity, and an SD/MMC interface (eMMC) to connect external flash memory for data logging or over-the-air update storage.
*'''Dedicated Processing Units:''' Some AURIX™ TC3xx models include special accelerators, such as a hardware Fast Fourier Transform unit (HW-FFT) and up to two Signal Processing Units (SPUs) optimized for radar signal processing. These enable the microcontroller to handle radar front-end data or other intensive DSP tasks (like Fourier transforms for radar or audio signals) on-chip, which is crucial for advanced driver assistance sensors. There is also a ''Security Module'' (covered in a later section) and a Safety Management Unit that supervise system integrity.
*'''Other On-chip Modules:''' Watchdog timers, error-correction coders for memories (ECC on flash and RAM for reliability), a programmable interrupt system, multiple DMA channels (up to 128 DMA channels) for efficient data movement, and debug interfaces (JTAG and a 2/3-pin DAP) for development. The on-chip debug system supports tracing of program execution (via a built-in Emulation Memory, MCDS) to aid in complex multicore software development.

Overall, the AURIX™TC3xx provides a highly integrated SoC-like platform, allowing a single chip to manage tasks ranging from powertrain control and chassis control to infotainment gateways. This high level of integration reduces the need for separate companion chips and helps to lower system complexity and cost.
===Performance and Benchmarking===
Fabricated in a 40 nm embedded flash process<ref name="ref2022357806" />, AURIX™ TC3xx processors achieve significant performance gains over prior generations while maintaining automotive-grade power efficiency. With six 32-bit cores at 300 MHz (four of them paired in lockstep), a flagship TC3xx device (e.g., TC39x) can deliver up to approximately 2,400 DMIPS of aggregate computing throughput<ref name="ref2022357806" />. In terms of per-core performance, the TriCore architecture yields around 1.3–2.0 DMIPS/MHz depending on the instruction mix, meaning each 300 MHz core can approach ~400–600 DMIPS in optimized scenarios<ref name="ref14281090103" /><ref name="ref1222155140">Infineon AURIX™ - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. This is on par with or exceeding many contemporary 32-bit automotive MCUs. The integrated DSP extensions and optional accelerators (like the FFT unit) also enable high-speed signal processing, with Infineon citing up to ~1.8 GFLOPS of DSP throughput for certain operations<ref name="ref1222155140" />.

Real-world performance improvements of the TC3xx over its predecessor are notable: for example, compared to the first-generation AURIX™ (which offered up to 740 DMIPS), the TC3xx’s expanded core count and clock speed provide roughly three times the computational power on the same type of workload<ref name="ref14281090103" />. This extra headroom allows more functions (such as running multiple control algorithms or sensor fusion tasks in parallel) to be consolidated onto one microcontroller without compromising real-time deadlines<ref name="ref14281090103" />. Despite the increase in speed and core count, the TC3xx family was designed with power and thermal constraints in mind, achieving these gains within similar power consumption envelopes as the previous generation by leveraging the smaller 40 nm process and power-saving features like clock gating<ref name="ref5727814512" />. The deterministic real-time performance (with features like lockstep and tightly-coupled memory) makes the AURIX™ TC3xx suitable for the most demanding automotive applications, where consistent low latency and high throughput are required simultaneously.

== On-Chip System Connectivity and Bridges ==
[[File:TC3xx On-Chip System Connectivity.png|thumb|The TC3xx has two '''SRI Domains''' (SRI0 and SRI1). CPU0 to CPU3 are connected to SRI0, CPU4/5 are connected to SRI1.|alt=TC3xx On-Chip System Connectivity|423x423px]]
The AURIX™ TC3xx Platform has three independent on-chip connectivity resources:

* '''System Resource Interconnect Fabric (SRI Fabric)''' connects the TriCore CPUs, the DMA module, and other high bandwidth requestors to high bandwidth memories and other resources for instruction fetches and data accesses. A key component of the fabric is the SRI crossbar, which connects all the agents in one SRI domain. The SRI crossbar carries the transactions between the SRI Masters and SRI Slaves of the domain. The SRI crossbar supports parallel transactions between different SRI Master and SRI Slave agents. In addition to the parallelism of concurrent requests, it also supports pipelined requests from an SRI Master to a SRI Slave.
* '''System Peripheral Bus (SPB)''' connects the TriCore CPUs, the DMA module, and other SPB masters to the medium and low bandwidth peripherals. SPB masters do not directly connect to the SRI Fabric, and will access SRI attached resources via a SFI_F2S Bridge.
* '''Back Bone Bus (BBB)''' connects the TriCore CPUs, the DMA module, and SPB masters with ADAS resources. SRI Masters do not directly connect to the BBB, but access BBB attached resources via a SFI_S2F Bridge. SPB masters also do not directly connect to the BBB, but access BBB attached resources via bridging over the SRI Fabric.

=== CPU Resource Access Times ===
These tables describe the CPU access times to various resources in CPU clock cycles for the AURIX™ TC3xx Platform. In the case of load or fetch accesses, the access times are the minimum number of CPU stall cycles to complete the access. If there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

For write access, the access times are the maximum for a sequence of such access (non-conflicting). In many cases for a singleton access, or a short sequence, write buffering reduces the stall effect seen by a CPU, sometimes to 0. However, as with loads and fetches, if there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

==== Access latency for global resources ====
{| class="wikitable"
|+
! CPU Access Type !! CPU stall cycles
!Notes
|-
| Data read from System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
| rowspan="2" |The final number of stall cycles will depend on the real number of WS generated by the target resource.
|-
| Data write to System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC39x, TC37xED) || <math>9 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
| rowspan="2" |When SFI_S2F is connected to XBar2 (TC39x and TC37xED) there is an additional latency due to access going through an S2S.
|-
| Data write to Back Bone Bus (BBB) (TC39x, TC37xED) || <math>5 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC35x, TC33xED) || <math>6 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
|
|-
| Data write to Back Bone Bus (BBB) (TC35x, TC33xED) || <math>3 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|
|}


* '''Module Wait State''': The number of wait states for read and for write accesses is >= 1 and depends on the accessed module and its configuration.


==== CPU Accesses: Stall cycles for local and SRI resources ====
{| class="wikitable"
|+
! CPU Access Type !! Local CPU !! Local SRI !! Remote SRI Domain
|-
| Data read from DSPR || 0 || 7 || 10
|-
| Data write to DSPR || 0 || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from DSPR || See local SRI column || 7 || 10
|-
| Data read from DLMU || 0 || 7 || 10
|-
| Data write to DLMU || 2 || 5, {{rev|3|with Pipelining}}|| 5, 4
|-
| Instruction fetch from DLMU || See local SRI column || 7 || 10
|-
| Data read from PSPR || See local SRI column || 7 || 10
|-
| Data write to PSPR || See local SRI column || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from PSPR || 0 || 7 || 10
|-
| Data read from PFlash || 5 + PWS || 10 + PWS || 13 + PWS
|-
| Instruction fetch from PFlash (buffer miss) || 2 + PWS || 9 + PWS || 12 + PWS
|-
| Instruction fetch from PFlash (buffer hit) || 3 || 6 || 9
|-
| Data read from LMU || n.a. || 7 || 10
|-
| Data write to LMU || n.a. || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from LMU || n.a. || 7 || 10
|-
| Data read from DFlash || n.a. || 5 + 3*(3 + DCWS) || 8 + 3*(3 + DCWS)
|-
| Data read access from EMEM (TC39x, TC37xED) || n.a. || n.a. || 14, {{rev|15|fBBB < fSRI}}
|-
| Data write access to EMEM (TC39x, TC37xED) || n.a. || n.a. || 9
|-
| Data read access from EMEM (TC35x, TC33xED) || n.a. || 11, {{rev|12|fBBB < fSRI}}|| n.a.
|-
| Data write access to EMEM (TC35x, TC33xED) || n.a. || 9 || n.a.
|-
| Data read access from DAM || n.a. || 10 || 13
|-
| Data write access to DAM || n.a. || 7 || 7
|}

* '''Remote SRI Domain''': Only applies to products with SRI extenders. Additional latency due to access going through an S2S
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''DCWS''': Configured DFlash Corrected Wait States (Includes cycles for DFlash access cycles and ECC correction latency)

== CPU Subsystem ==
[[File:TC3xx Processor Core, Local Memory and Connectivity.png|alt=TC3xx Processor Core, Local Memory and Connectivity|thumb|Processor Core, Local Memory and Connectivity]]The Infineon AURIX™ TC3xx features up to 6 processor cores (CPU0 ... CPU5) implementing the [[TriCore Instruction Set Architecture|TC1.6.2 instruction set architecture]]. The following section focuses on the microarchitectural details of the CPU subsystem. For more information about the ISA, please take a look at the [[TriCore Instruction Set Architecture]].

The processor core connects to the following memories and bus interfaces (where implemented):
*Program Scratch-Pad SRAM (PSPR)
*Data Scratch-Pad SRAM (DSPR)
*Program Cache (PCache)
*Data Cache (DCache)
*Local Memory Unit (DLMU)
*Local Pflash bank (LPB)
*SRI slave interface (x2)
*SRI master Interface
*SPB master interface

=== TC1.6.2P Implementation Features ===
*Most instructions executed in 1 cycle
*Branch instructions in 1, 2 or 3 cycles (using dynamic branch prediction)
*Wide memory interface for fast context switch
* Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
*Six memory protection register sets
*Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
*Third pipeline for loop instruction only (zero overhead loop)
*Single precision Floating Point Unit (IEEE-754 Compatible)
*Dedicated Integer divide unit
*18 data memory protection ranges, 10 code memory protection ranges arranged in 6 sets

=== Superscalar Architecture ===
The processor core within the AURIX™ TC3xx family, specifically the TC1.6.2P implementation, employs a superscalar architecture characterized by three parallel pipelines: the Integer Pipeline, the Load/Store Pipeline, and the Loop Pipeline. Superscalar execution is a form of instruction-level parallelism that enables the processor to issue and execute multiple instructions during a single clock cycle. The TriCore TC3xx core's superscalar architecture allows it to issue and execute multiple instructions in parallel. Specifically, it can issue up to two instructions simultaneously to the Integer and Load/Store pipelines. However, there are certain constraints on this dual issuing capability. For example, back-to-back data arithmetic instructions can only be issued in separate cycles, and a load/store instruction can be issued either on its own or paired with a data arithmetic instruction, provided the load/store instruction is the second in the pair. Under ideal conditions, with careful instruction scheduling, this dual-issue capability can lead to a throughput of close to 0.5 clock cycles per instruction, effectively executing two instructions per cycle.

=== Pipeline Stages ===
The execution of instructions within the TriCore TC3xx core is managed through a pipeline consisting of several stages. In one document it is mentioned that the pipeline consists of 6 stages <ref name="ref3635926" />, but the exact stages remain unclear. From the architecture the following stages can be inferred:

* '''Fetch Stage''': The initial stage in the pipeline is the Fetch stage, where instructions are retrieved from memory. This task is handled by the Instruction Fetch Unit (IFU), which is responsible for fetching instructions from the memory system. To improve efficiency, the IFU employs a pre-fetching mechanism, anticipating the instructions that will be needed and bringing them into the processor before they are actually required. Instructions are fetched through a 64-bit wide Program Memory Interface (PMI), allowing for the retrieval of a significant amount of instruction data in each cycle. The fetched instructions are then placed into an issue FIFO, a buffer capable of holding up to six instructions. This buffer plays a crucial role in managing the flow of instructions to the subsequent execution pipelines. The 64-bit fetch width and the instruction buffer are indicative of a design that aims to ensure a continuous supply of instructions to the pipelines, preventing them from being starved of work. A wider fetch path allows for more instruction bits to be obtained from memory in each clock cycle, while the buffer helps to mitigate temporary delays in instruction fetching.
* '''Execution Unit''': The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop Pipeline. All three pipelines operate in parallel and are capable of executing instructions simultaneously. Each pipline has its own decode stage and two execute stages. Furthermore, the TC3xx features a Floating Point Unit (FPU). It is not clear whether the FPU is part of the execution unit or a separate unit. It is assumed that the FPU also has its own decode stage and an unknown number of execute stages
** '''Decode Stage''': Following the Fetch stage, the instruction are issued to one of the pipelines. In the decode stage of each pipeline, the instruction is examined and translated to determine the specific operation it represents and to identify the operands it will operate on. It is assumed that operands are read from the register file during the decode stage.
** '''Execute Stage''': The Execute stage is where the actual operation specified by the instruction is carried out. Pipeline hazards (stalls) are minimised by the use of forwarding paths between pipeline stages allowing the results of one instruction to be used by a following instruction as soon as the result becomes available.
** '''Writeback Stage''': The final stage in the pipeline is the Writeback stage. In this stage, the results produced by the executed instruction are written back to the processor's register file, making them available for subsequent instructions. It is unclear whether the writeback stage is part of the (two) execution stages or a separate stage.

=== Execution Pipelines ===
The TriCore TC3xx core leverages four parallel pipelines to enhance its performance. Each pipeline is designed to handle a specific class of instructions:

* '''Integer Pipeline:''' This pipeline is responsible for executing integer arithmetic and logical instructions, including data-conditional jump instructions, bit manipulation operations, as well as division and multiply-accumulate (MAC) instructions.
* '''Load/Store Pipeline:''' The primary function of this pipeline is to manage memory access operations, including loading data from memory and storing data to memory. It also handles address arithmetic, unconditional jump instructions, procedure call instructions, context-switching operations, and control flow related to context save areas (CSAs).
* '''Loop Pipeline:''' This is a specialized pipeline designed to facilitate zero-overhead loops, a technique that significantly improves the performance of iterative code sections. Its design aims to eliminate or minimize the overhead typically associated with loop control, such as incrementing counters and checking loop conditions. Some documentation suggests that the loop pipeline comes along with a "Loop Cache". This dedicated cache would likely be used to store instructions belonging to the loop, enabling very fast access and execution for repeated iterations.
* '''Floating Point Unit (FPU):''' The FPU is responsible for executing floating-point arithmetic operations

=== Store Buffers ===
The TriCore TC3xx core include '''Store Buffers''' to decouple memory write operations from CPU instruction execution. All stores from the Load/Store Pipeline are placed in the store buffer prior to being written to local memory or transferred via the bus system. Write data is taken from the store buffers and written to memory when the target memory or bus interface becomes available. In normal operation the CPU will prioritise memory load operations over store operations in order to improve performance unless the store buffer is full or the order of load and store operations must be preserved (e.g. peripheral space access). The store buffer can hold the data for up to 6 stores operations. To improve performance the store buffer will merge consecutive byte, half-word, and word writes of the same location to reduce the number of memory accesses required.

=== Instruction Timing ===

==Functional Safety and Security Features==
===Hardware Security Module and Encryption===
One of the defining features of the AURIX™ TC3xx family is its robust hardware-based security subsystem, implemented to protect against cyber threats and unauthorized manipulation of vehicle systems. Each TC3xx MCU includes a dedicated ''Hardware Security Module'' (HSM), which is essentially an on-chip co-processor with its own CPU and cryptographic engine designed to handle secure operations. In the second-generation AURIX™ (TC3xx), the HSM was upgraded with support for asymmetric cryptography (e.g., RSA, ECC algorithms) in hardware, providing significantly faster public-key encryption and authentication capabilities than pure software implementations. This HSM supports '''EVITA Full''' (the highest level of the EU’s EVITA automotive security requirements), meaning it can perform secure boot, message authentication, and encryption at a level suitable for protecting critical in-vehicle communications. For example, the HSM can encrypt and authenticate CAN/Ethernet messages to prevent spoofing or tampering on the vehicle network, and it can manage cryptographic keys securely isolated from the main application cores.<ref name="ref14281090104">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref2022357806" />

The security module enables features like '''secure boot''', where the AURIX™ will only execute firmware that is digitally signed by the vehicle manufacturer, thereby preventing unauthorized or malicious code. It also facilitates ''over-the-air (OTA) updates'' in a secure manner: the TC3xx HSM can verify and decrypt update packages received via telematics, allowing firmware upgrades while protecting against attackers attempting to hijack the software. In addition, the HSM includes a true random number generator and supports protocols for immobilizer and theft protection systems. Infineon’s implementation essentially treats the HSM as an “embedded smart card” inside the microcontroller. This approach, building on Infineon’s expertise in chip card security, helps to safeguard sensitive assets like cryptographic keys and to perform secure operations (encryption, decryption, authentication) in hardware, making attacks significantly more difficult. The strong cybersecurity provisions of the AURIX™ TC3xx have made it a preferred choice for vehicle gateway ECUs and central body controllers, which are points of entry for connected car communications and thus high-value targets for hackers. By incorporating the HSM, automotive OEMs can implement advanced security features such as encrypted onboard communication (to thwart bus tampering) and secure diagnostics, ensuring the vehicle’s electronic data is protected against cyber threats even as cars become more connected.<ref name="ref14281090104" /><ref name="ref5727814513">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref><ref name="ref19484776953">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
=== Functional Safety and Fault Tolerance===
Beyond cybersecurity, the AURIX™ TC3xx architecture is built with extensive ''functional safety'' features to meet the highest safety integrity levels in automotive systems. The multi-core design supports ''lockstep operation'', where redundant checker cores run in parallel with main cores and continuously compare results cycle-by-cycle. In TC3xx devices, up to four of the six TriCore CPUs have such lockstep partner cores, allowing the microcontroller to detect any single-point CPU failure instantly (if a discrepancy arises between the core and its checker, a fault is signaled). A ''Safety Management Unit (SMU)'' is integrated on-chip to monitor various fault conditions throughout the device – it aggregates error signals from the lockstep cores, memory ECC monitors, clock/watchdog monitors, and peripheral self-tests, and can initiate safe-state actions (like resetting the chip or signaling an error pin to an external supervisor) if a critical fault is detected. The AURIX™ safety concept also includes a distributed Memory Protection Unit (MPU) arrangement, with multiple memory protection contexts that prevent errant or malicious code from writing to wrong memory areas. This helps contain faults and eases the integration of software with mixed criticality (Infineon allows partitioning software components of different ASIL levels on the same MCU while keeping them isolated).<ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref19519075552">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX™ https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref>

Crucially, the TC3xx family was developed according to ISO 26262 processes and can achieve '''ASIL-D''' (Automotive Safety Integrity Level D), the highest grade for automotive functional safety. Compared to a traditional dual-core lockstep approach, the AURIX’s™ multi-core safety architecture allowed Infineon to reduce certain safety development overheads (earlier Infineon data suggested up to 30% reduction in safety software workload) by providing built-in safety mechanisms and diagnostics. Infineon supplies a comprehensive safety manual and diagnostic libraries for the AURIX™, helping engineers utilize features like CPU self-tests, RAM tests, and CRC checks to comply with safety standards. In addition to automotive standards, the AURIX™ TC3xx has also been qualified for '''industrial safety''': in 2023, Infineon announced support for IEC 61508 metrics, enabling designs with AURIX™ to reach SIL-2 and SIL-3 safety integrity levels for industrial applications. This cross-industry safety compliance is facilitated by the MCU’s redundant design and detailed failure mode documentation (FMEDA) provided by Infineon. In summary, the AURIX™ TC3xx integrates both proactive safety (fault prevention via lockstep, monitoring and protection) and reactive safety (fault detection and safe shutdown), making it a dependable component for systems that cannot afford unintended behavior, whether in cars, factories, or aerospace. <ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref4967712052">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref><ref name="ref196858272">MCUs support industrial functional safety - Electronic Products https://www.electronicproducts.com/mcus-support-industrial-functional-safety/</ref>
== Platform Devices ==
The following table shows a feature overview of the AURIX™ TC3xx Platform family focusing on memory and number of cores.
{| class="wikitable"
!
!Feature
!TC33x
!TC33xEXT
!TC35x
!TC36x
!TC37x
!TC37xEXT
!TC38x
!TC39x
|-
| rowspan="2" |CPUs
|Cores / Checker Cores
|1 / 1
|2 / 1
|3 / 2
|2 / 2
|3 / 2
|3 / 3
|4 / 2
|6 / 4
|-
|Max. Freq.
| colspan="8" |300 MHz
|-
| rowspan="2" |Cache per CPU
|Program [KB]
| colspan="8" |32
|-
|Data [KB]
| colspan="8" |16
|-
| rowspan="3" |SRAM per CPU
|PSPR [KB]
|8
|{{rev|32|CPU0}}
{{rev|64|other}}
|64
|32
|64
|64
|64
|64
|-
|DSPR [KB]
|192
|{{rev|192|CPU0}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|192
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|-
|DLMU [KB]
|8
|{{rev|8|CPU0}}
{{rev|64|other}}
|64
|64
|64
|64
|64
|64
|-
| rowspan="2" |SRAM global
|LMU [KB]
| -
| -
|512
| -
| -
| -
|128
|768
|-
|DAM [KB]
| -
| -
|32
| -
|64
|64
|128
|128
|-
| rowspan="3" |Extension Memory (EMEM)
|TCM [MB]
| -
|1
|2
| -
| -
|2
| -
|2
|-
|XCM [MB]
| -
| -
| -
| -
| -
|1
| -
|2
|-
|XTM [KB]
| -
|16
|16
| -
| -
|16
| -
|16
|-
| rowspan="2" |Program Flash
|Size [MB]
|2
|4
|4
|4
|6
|10
|10
|16
|-
|Banks [MB]
|1 x 2
|2 x 2
|2 x 2
|2 x 2
|2 x 3
|3 x 3, 1 x 1
|3 x 3, 1 x 1
|5 x 3, 1 x 1
|-
| rowspan="2" |Data Flash
|DF0 Size (single-ended) [KB]
|128
|128
|128
|128
|256
|512
|512
|1024
|-
|DF1 Size (single-ended) [KB]
|128
|128
|128
|128
|128
|128
|128
|128
|-
| rowspan="3" |DMA
|Channels
|64
|64
|64
|64
|128
|128
|128
|128
|-
|Move Engines
|2
|2
|2
|2
|2
|2
|2
|2
|-
|Resource Partitions
|4
|4
|4
|4
|4
|4
|4
|4
|}

== Compilers ==
The AURIX™ TC3xx family is a series of high-performance microcontrollers widely used in automotive and industrial applications. Compilers for the AURIX™ TC3xx are crucial for developers aiming to optimize performance, reliability, and safety in their applications. One significant aspect of the compiler landscape for AURIX™ TC3xx is the limited direct support from mainline open-source compilers such as GCC or LLVM/Clang. The primary reason for this is the stringent requirements for functional safety in automotive and industrial applications, which demand specialized features and compliance with safety standards that are often not met by general-purpose open-source compilers.

=== Commercial Compilers ===

# '''Tasking''': Tasking compilers are renowned for their robust support for automotive applications, offering advanced debugging capabilities and optimization techniques tailored for the AURIX™ architecture. They provide extensive code optimization, comprehensive debugging tools, and strong support for safety standards such as ISO 26262, making them ideal for developing high-performance, reliable, and safe applications.
# '''HighTec''': The HighTec compiler is a popular choice, known for its Eclipse-based development environment and strong multicore support. HighTec provides both GCC and LLVM-based ports of open-source compilers tailored specifically for the AURIX™ TC3xx family. These compilers offer efficient parallel execution, advanced code analysis, and an integrated development environment, ensuring robust performance and compliance with safety standards.
# '''Green Hills Software''': Green Hills Software provides a highly optimized toolchain aimed at safety-critical applications, focusing on high performance and strict compliance with automotive standards. Their compiler offers superior optimization, extensive safety features, and a proprietary IDE with specialized tools for automotive development, ensuring developers can meet the stringent demands of functional safety.

=== GCC for AURIX™ ===

While mainline GCC does not directly support the AURIX™ TC3xx family, there is an unofficial GCC version available for AURIX™. Due to the GNU General Public License (GPL), the source code from HighTec was retrieved and, along with binary versions, published on GitHub:

*GCC 4.9.4/Binutils 2.20/Newlib 1.18 for Tricore AURIX™ [[https://github.com/volumit/package_494 Source]] [[https://github.com/volumit/tricore_gcc494_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc494_linux_bins Prebuild Linux Binaries]]
*GCC 9.4.0/Binutils 2.20/Newlib 1.18 for Tricore AURIX™ [[https://github.com/volumit/package_940 Source]] [[https://github.com/volumit/tricore_gcc940_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc940_linux_bins Prebuild Linux Binaries]]
*GDB 10.0.50 for Tricore AURIX™ [[https://github.com/volumit/gdb-tricore Source]]
==emmtrix Tools for AURIX™ TC3xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX™ TC3xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

==See Also==

*[[Infineon AURIX TC4x|Infineon AURIX™ TC4x]]
*[[Infineon AURIX TC2xx|Infineon AURIX™ TC2xx]]
*[[TriCore Instruction Set Architecture]]

==External Links==

*https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/
*[https://documentation.infineon.com/aurixtc3xx/docs/qmd1702366622648 AURIX™ TC3xx user manuals]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d3605221d96 AURIX™ TC3xx User Manual Part-1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d35f8541d94 AURIX™ TC3xx User Manual Part-2]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd AURIX™ TC3xx Architecture vol 1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 AURIX™ TC3xx Architecture vol 2]

== References ==
<references />
[[Category:Supported Architectures]]

{{#seo:
|title=Infineon AURIX TC3xx Family – Deep Dive
|description=This deep dive into Infineon's AURIX TC3xx family explores its multi-core TriCore architecture, real-time capabilities, safety and security features and tools
|image=File:AURIX_TC399_LFBGA-516_plain.jpg
|keywords=AURIX, Infineon, TC3xx, microcontroller, TriCore, automotive, ADAS, ISO 26262, functional safety, embedded security, ASIL-D, deep dive
}}

Infineon AURIX TC2xx

2025-04-08T07:45:28Z

Mira.steinmetz:

'''Infineon AURIX™ TC2xx''' is a family of 32-bit automotive microcontrollers developed by Infineon Technologies. ''AURIX™'' stands for ''“Automotive Realtime Integrated Next Generation Architecture”'', reflecting its design for real-time, safety-critical automotive applications<ref name="ref1222155140">Infineon AURIX™ - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. The TC2xx series (first-generation AURIX™) is based on a multicore architecture featuring up to three independent 32-bit '''TriCore™''' processor cores. Introduced around 2012, the AURIX™ TC2xx marked Infineon’s transition to a multicore microcontroller platform (fabricated in 65 nm technology) after earlier single-core TriCore™ generations. It was designed from the ground up to meet stringent automotive safety requirements (ISO 26262) and to provide higher performance and integration for applications like engine management, chassis control, and driver assistance systems.<ref name="ref1222155140" /><ref name="ref1490396573">Optimized for Success - EE Times Europe https://www.eetimes.eu/optimized-for-success/</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>

The AURIX™ TC2xx family’s design philosophy is to combine '''safety''', '''security''', and '''performance''' in one scalable MCU platform. It achieves high functional safety compliance (up to '''ASIL-D''', the highest automotive safety integrity level) with less development effort compared to traditional dual-controller lockstep systems<ref name="ref572781451" />. Infineon claims that using AURIX™ can cut safety-related development time by ~30% versus classical lockstep architectures, thanks to its built-in fault detection and monitoring hardware. At the same time, the TC2xx provides significant performance headroom – roughly 50% to 100% higher computational performance compared to its predecessors – while maintaining power consumption similar to previous single-core designs. To address emerging automotive security needs, the AURIX™ MCUs also integrate a dedicated Hardware Security Module ('''HSM''') on-chip, which protects against IP theft, fraud, and tampering. This combination of features makes the AURIX™ TC2xx a popular choice for consolidating various automotive control functions (powertrain, safety, body, etc.) onto one platform, without sacrificing reliability or efficiency.<ref name="ref572781451" /><ref name="ref71179009">32-bit TriCore™ AURIX™– TC2xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/</ref>
==Architecture==
The AURIX™ TC2xx is built on Infineon’s '''TriCore™''' architecture, which uniquely unifies traits of a RISC processor, a microcontroller, and a DSP (digital signal processor) into one core design. Each TriCore™ CPU in the TC2xx is a 32-bit superscalar processor that supports both 32-bit and 16-bit instruction formats (the latter for code size efficiency). The TriCore™ instruction set architecture includes typical RISC features (load/store architecture, 4 GB address space) and DSP capabilities (such as multiply-accumulate instructions and bit manipulation) in a single core. The cores also have an optional floating-point unit (FPU) and support SIMD (single-instruction multiple-data) operations for signal processing acceleration. The maximum core frequency in the TC2xx family is 300 MHz, and devices achieve about 1.7–2.4 DMIPS/MHz per core, providing robust real-time performance.<ref name="ref1222155140" /><ref name="ref71179009" />

In terms of core configuration, high-end AURIX™ TC2xx models implement three main TriCore™ CPUs, which can be run in parallel or in redundant (lockstep) pairs for safety. Some variants include a redundant checker core that shadows a primary core to detect calculation errors (a technique to meet SIL/ASIL safety goals). The multicore architecture is supported by a layered memory system: each TriCore™ has tightly coupled local memory for fast instruction and data access, and they share access to large on-chip Flash and RAM via an internal bus matrix. Memory options in the TC2xx range from about '''0.5 MB up to 8 MB of on-chip Flash''', and from ~50 KB up to 2.7 MB of SRAM, depending on the specific device. This on-chip memory (with ECC protection on memories for safety) allows real-time code execution and data storage without external memory in most use cases. For peripherals and I/O, the AURIX™ architecture includes a rich set of on-chip modules connected via internal buses, such as analog-to-digital converters, timer units, communication interfaces, and direct memory access (DMA) controllers. AURIX™ TC2xx MCUs typically provide interfaces like multiple CAN/CAN-FD channels, LIN/UART, SPI, I²C, Ethernet (on higher-end models), and automotive-specific buses (e.g. FlexRay on some variants), making the chip a self-contained controller for complex automotive networks.'''<ref name="ref572781451" />'''<ref name="ref71179009" /><ref name="ref957370148">Infineon TriCore™ - Wikipedia https://en.wikipedia.org/wiki/Infineon_TriCore</ref>

The '''Generic Timer Module (GTM)''' is a notable part of the AURIX™ TC2xx architecture. It is a sophisticated timer/co-processor integrated on-chip to handle complex timing, PWM generation, input capture, and other signal conditioning tasks across more than 200 channels. There are also specialized accelerators and co-processors on certain TC2xx devices, such as a '''Hardware Fast Fourier Transform (HFFT)''' unit for signal processing and a '''Parallel Pixel Processor''' for simple video or sensor data processing. These dedicated engines offload the TriCore™ CPUs for specific high-load tasks (e.g. radar signal FFTs or encoder signal processing), improving overall throughput in automotive applications. The AURIX™ architecture uses a single-power supply (5V or 3.3V) design and includes an on-chip voltage regulator (EVR), simplifying power management. The MCUs are offered in a variety of package types (from compact QFP-64 up to large BGA-516) to accommodate different I/O needs. Overall, the TC2xx architecture is highly integrated and optimized for real-time, combining multiple CPU cores with ample flash memory, SRAM, and peripherals on one chip to serve as a '''central control unit''' in vehicles.<ref name="ref1222155140" /><ref>AURIX™ Unleashed - RS Components https://docs.rs-online.com/0f3f/0900766b815c315c.pdf</ref>
====CPU access latency (TC29x) ====
{| class="wikitable"
!CPU Access Type!!Local CPU
|-
|Data read access to own DSPR||0
|-
|Data write access to own DSPR||0
|-
|Data read access to own or other PSPR||8
|-
|Data write access to own or other PSPR||0
|-
|Data read access to other DSPR||8
|-
|Data write access to other DSPR||0
|-
|Instruction fetch from own PSPR
|0
|-
|Instruction fetch from other PSPR (critical word)||8
|-
|Instruction fetch from other PSPR (any remaining words)||0
|-
|Instruction fetch from other DSPR (critical word)||8
|-
|Instruction fetch from other DSPR (any remaining words)||0
|-
|Initial Pflash Access (critical word)||7 + configured PFlash Wait States
|-
|Initial Pflash Access (remaining words)||0
|-
|PMU PFlash Buffer Hit (critical word)||6
|-
|PMU PFlash Buffer Hit (remaining words)||0
|-
|Initial Dflash Access||7 + configured DFlash Wait States
|-
|TC1.6P Data read from System Peripheral Bus (SPB)
|{{rev|4|2=fCPU = fSPB}} {{rev|7|2=fCPU = 2*fSPB}} {{rev|10|2=fCPU = 3*fSPB}}
|-
|TC1.6P Data write to System Peripheral Bus (SPB)||0
|}
*

==Key Features==

* '''Safety Mechanisms:''' The AURIX™ TC2xx was developed via an ISO 26262-compliant process and includes multiple hardware mechanisms to achieve '''functional safety up to ASIL-D'''. Notably, it supports ''lockstep'' operation, where one or two of the TriCore™ CPUs can run in redundant lockstep mode with another core to detect discrepancies (faults) cycle-by-cycle. A Safety Management Unit ('''SMU''') is built in to monitor critical system parameters and handle faults. The architecture employs memory protection units and safe internal communication buses to isolate and supervise different software domains. Other safety features include '''error-correcting code (ECC)''' on flash and RAM, redundant peripherals (for example, duplicated ADC channels), watchdog timers, clock and voltage monitors, and self-test routines. These features allow developers to more easily implement safety-critical functions and meet standards like IEC 61508 (SIL-3) or ISO 26262 (ASIL-D) using a single AURIX™ MCU, whereas achieving the same on a traditional single-core MCU might require additional external safety ICs or companion processors.<ref name="ref1490396573" /><ref name="ref572781451" />
* '''Security Functions:''' Infineon integrated a dedicated Hardware Security Module ('''HSM''') into the AURIX™ TC2xx family to address automotive cybersecurity requirements. This HSM is essentially an on-chip co-processor (with its own CPU and flash) that handles cryptographic operations and secure key storage isolated from the main cores. It follows the EVITA (E-safety Vehicle Intrusion Protected Applications) guidelines for automotive security. The HSM enables features like secure boot, encryption/decryption, authentication, and detection of software tampering. By having a built-in “embedded smart card” for security, the AURIX™ can implement anti-theft, anti-cloning, and secure onboard communication measures without needing an external security chip. This integration is a key differentiator, as it helps protect vehicle functions (e.g. immobilizers, firmware updates, V2X communication) against hacking and unauthorized modifications.<ref name="ref1222155140" /><ref name="ref71179009" />
* '''Performance and DSP Capability:''' Each TriCore™ CPU in the TC2xx is capable of up to 300 MHz operation, and combined the multicore setup offers considerable processing power for an MCU (Infineon cites up to ~1.8 GFLOPS of DSP throughput for the highest models). The TriCore™ design delivers around '''1.7–2.4 DMIPS/MHz''' per core, meaning a triple-core AURIX™ at max frequency can exceed 2000 DMIPS of total throughput. The inclusion of DSP instructions and dedicated accelerators enables the AURIX™ to handle computationally intensive tasks (like control algorithms, filtering operations, or even rudimentary neural networks) that previously might require a separate DSP or FPGA. A built-in '''Floating Point Unit''' on each core supports single-precision (and optional double-precision in some cases) arithmetic, beneficial for model-based control algorithms and automotive sensor processing. Peripherals like the '''Generic Timer Module (GTM)''' and '''Hardware FFT''' accelerator (available on select TC2xx variants) further boost real-time performance for handling high-frequency events (e.g. engine ignition timing, motor control PWM, radar signal analysis) without overloading the CPU. Despite the performance, the TC2xx was designed with efficiency in mind; Infineon managed to double the performance over the prior generation (TC1xx AUDO) while keeping power consumption at comparable levels. The MCUs also support various low-power modes and a standby controller to minimize energy usage when parts of the system are idle.<ref name="ref1222155140" /><ref name="ref572781451" />
* '''Power and Integration:''' As a system-on-chip for vehicles, AURIX™ TC2xx integrates a wide range of '''communication interfaces''' and analog/digital peripherals. Common features include multiple CAN bus controllers (often with CAN FD support), LIN/UART, SPI and I²C channels, FlexRay communication in high-end models, and even Ethernet (in variants aimed at gateway or ADAS roles). High-resolution '''ADC units''' (with shared and redundant channels) allow precise sensor measurements for engine or chassis control. There are also specialized modules like delta-sigma ADCs and SENT interfaces for automotive sensor inputs. This rich peripheral set reduces the need for external components, helping to lower the overall system Bill of Materials. The TC2xx devices operate over a broad temperature range (typically –40 °C to +150 °C), meeting the demands of under-the-hood automotive environments. They run from a single supply (with internal regulators), simplifying designs, and support both 5 V and 3.3 V systems for compatibility with a variety of sensors and actuators. Combined with its safety and security features, the AURIX’s™ high integration makes it a one-chip solution for many complex embedded applications.<ref name="ref1222155140" /><ref name="ref1490396573" /><ref name="ref71179009" /><ref name="ref957370148" />

==Applications==
The Infineon AURIX™ TC2xx family is primarily targeted at the '''automotive industry''', especially domains requiring high reliability and real-time control. Its initial use cases were in '''powertrain''' and engine management systems – for example, controlling combustion engines, managing fuel injection and ignition, and coordinating electric motor and battery systems in hybrid or electric vehicles. The multi-core AURIX™ can run multiple control algorithms in parallel (e.g. for an engine’s cylinders, transmission and motor inverter concurrently), which is valuable in modern electrified powertrains. Beyond engines, AURIX™ TC2xx MCUs are used in '''chassis and safety systems''': they can serve as the central controller for '''anti-lock braking systems (ABS)''' and stability control, '''airbag control units''', '''electric power steering (EPS)''' systems, and suspension controllers. Advanced Driver Assistance Systems ('''ADAS''') and autonomous driving modules in earlier generations of vehicles have also employed AURIX™ for tasks such as sensor fusion, radar signal processing, and acting as a safety supervisor for driving assistance features<ref name="ref572781451" />. For example, a radar unit for adaptive cruise control might use an AURIX™ to perform real-time signal processing (using its DSP capabilities and HFFT) and make high-level decisions, all within an ASIL-D safe environment.<ref name="ref572781451" /><ref name="ref1228701036">https://resources.tasking.com/sites/default/files/2021-02/Take%20Advantage%20of%20Infineon%20AURIX%20TC3xx%20Family%20With%20the%20Right%20Compiler_WEB.pdf</ref>

Thanks to its safety certification and robust design, the AURIX™ TC2xx has seen adoption in any application that cannot tolerate failure. This includes '''industrial automation and robotics''', where the MCU’s reliability and support for functional safety (IEC 61508) are attractive. In industrial motor drives or robotics controllers, an AURIX™ might handle precise motor control algorithms and system monitoring. Other use cases outside pure automotive include '''commercial vehicles and transportation''' (trucks, agricultural and construction machinery), which have similar safety and durability requirements. The AURIX’s™ extensive communication interfaces also make it suitable as a gateway or central node in complex networks – for instance, acting as a domain controller in modern automotive E/E architectures to coordinate data between powertrain, body, and ADAS subsystems. Some '''electric vehicle (EV)''' platforms use AURIX™ MCUs in battery management systems and inverter controls, leveraging its calculation power for battery algorithms and its safety for monitoring cell health. In summary, the TC2xx family finds use in scenarios that demand '''real-time performance with high safety integrity''', predominantly in automotive (engine, transmission, chassis, safety, ADAS) but also in high-end industrial embedded systems.<ref name="ref71179009" /><ref name="ref1228701036" />

==emmtrix Tools for AURIX™ TC2xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX™ TC2xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ TC2xx / [[Infineon AURIX TC3xx|TC3xx]]/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

== See Also ==

* [[Infineon AURIX TC3xx|Infineon AURIX™ TC3xx]]
* [[Infineon AURIX TC4x|Infineon AURIX™ TC4x]]
* [[TriCore Instruction Set Architecture|TriCore™ Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/
* [https://www.infineon.com/dgdl/Infineon-TC29x_B-step-UM-v01_03-EN.pdf?fileId=5546d46269bda8df0169ca1bdee424a2 TC29x B-Step User Manual]

== References ==
<references />
[[Category:Supported Architectures]]

Infineon AURIX TC3xx

2025-04-08T07:33:49Z

Mira.steinmetz:

[[File:AURIX TC399 LFBGA-516 plain.jpg|thumb|Infineon AURIX™ TC3xx second-generation microcontroller (TC399 BGA package). The AURIX™ TC3xx family integrates multiple TriCore CPUs and on-chip safety/security modules for automotive applications.|alt=TC399 BGA package]]
The '''Infineon AURIX™ TC3xx''' (Automotive Realtime Integrated neXt-generation architecture) is a family of 32-bit automotive microcontrollers introduced as the second generation of Infineon’s AURIX™ platform. Launched in 2016 as a successor to the earlier [[Infineon AURIX TC2xx|AURIX™ TC2xx series]], the TC3xx devices emphasize high performance, functional safety, and embedded security for advanced automotive and industrial applications. AURIX™ TC3xx microcontrollers feature a hexa-core [[TriCore Instruction Set Architecture|''TriCore'' processor architecture]] with enhanced safety measures, making them well-suited for demanding tasks such as autonomous driving domain controllers, powertrain control, and sensor data fusion in advanced driver-assistance systems (ADAS). The combination of multiple CPU cores, extensive on-chip memory, and a rich peripheral set allows TC3xx chips to deliver real-time responsiveness and reliability in safety-critical environments while meeting stringent automotive standards (such as ISO 26262 for functional safety).<ref name="ref1951907555">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref><ref name="ref1428109010">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref1948477695">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
==Applications==
AURIX™ TC3xx microcontrollers are used in a variety of safety-critical and high-performance applications across the automotive and industrial sectors. Key application domains include:
*'''Automotive Systems:''' The TC3xx family was primarily designed for automotive use and finds broad application in vehicles’ electronic control units (ECUs). Notably, it is used in ''powertrain and drivetrain control'' (engine management, transmission control, hybrid/electric vehicle inverter control, battery management) where its real-time processing and resilience support precise actuator control. It is also deployed in ''chassis and safety systems'' such as anti-lock braking systems (ABS), electronic stability control, airbag controllers, and electric power steering, leveraging its redundancy and fast response for fail-safe operation. With the growth of ADAS and autonomous driving, AURIX™ TC3xx devices serve as domain controllers for ''ADAS sensor fusion'', handling data from radar, LiDAR, camera, and ultrasonic sensors and performing environment modeling and decision-making algorithms. Their combination of multiple cores and a built-in radar signal processing sub-system makes them an attractive choice for tasks like front radar processing, sensor fusion hubs, and ''autonomous driving domain controllers'' that must meet ASIL-D safety levels.<ref name="ref14281090102">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
*'''Industrial Automation and Robotics:''' Infineon has also positioned the AURIX™ family for use in industrial applications that demand high reliability. The TC3xx MCUs, with their hardware self-test mechanisms and safety documentation, can be found in ''industrial motor drives, robotics controllers, and PLCs (programmable logic controllers)'', where they help achieve functional safety certifications up to SIL-3 (according to IEC 61508). The powerful TriCore cores and rich peripheral set enable complex motor control algorithms (e.g., field-oriented control for servo motors) and real-time sensor processing in factory automation. Additionally, the support for automotive-grade networking (CAN/CAN-FD, Ethernet) and timing peripherals makes them suitable for synchronous control in robotics and machinery. Infineon’s provision of AUTOSAR-compatible software for AURIX™ has even facilitated its use in non-automotive settings such as medical devices and elevator controllers, where proven safety and security are required.<ref name="ref496771205">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref>
*'''Aerospace and Defense:''' The high fault-tolerance and deterministic performance of the AURIX™ TC3xx architecture also attract interest for aerospace and other mission-critical uses. In avionics systems or autonomous drones, for instance, the lockstep core configuration and robust error checking of AURIX™ can provide an added layer of reliability for flight control computers or navigation systems. While primarily an automotive chip, its ability to operate in harsh conditions (−40°C to 150°C range) and to detect internal failures in real-time makes it viable for certain aerospace electronic systems. Some defense and aerospace projects leverage COTS (commercial off-the-shelf) automotive components like AURIX™ for applications such as unmanned vehicle control and high-reliability communication links, given its safety pedigree. (In these domains, additional analysis and possibly radiation testing would be performed if the devices are used in high-altitude or space environments.)
== Architecture Overview ==
[[File:Infineon TC3xx Architecture.webp|545x545px|thumb|alt=TC3xx Architecture Overview|TC3xx Architecture Overview]]
=== Processor Cores and Architecture===
The AURIX™ TC3xx family implements Infineon’s TriCore™ architecture, which uniquely combines aspects of RISC microcontrollers, DSP (digital signal processor) capabilities, and conventional microprocessor features into a single core design. Each TC3xx device can include up to six independent TriCore 32-bit CPU cores (TriCore version 1.6.2), all capable of running at up to 300 MHz clock frequency. Four of these cores can operate in dual-core lockstep pairs (with one core acting as a redundant checker for its partner) to provide fault detection for safety-critical functions. The TriCore cores use a superscalar Harvard architecture with 32-bit instruction words (and support for mixed 16/32-bit instruction encoding for code density). Each core includes a dedicated Floating Point Unit (FPU) for single-precision arithmetic and supports DSP-oriented instructions (e.g. single-cycle 16×16 MAC operations, SIMD for 16-bit/8-bit data) to accelerate signal processing tasks. For fast real-time performance, the architecture offers low interrupt latency (with automatic context save on-chip) and features like zero-overhead loops and a programmable peripheral timer unit for scheduling tasks. In total, a high-end TC3xx (such as the TC39x) provides six 300 MHz cores plus four checker cores, yielding a theoretical processing throughput of up to ~2400 DMIPS (Dhrystone MIPS) when all cores are utilized. This represents roughly a threefold increase in computational power over the previous AURIX™ generation (which achieved ~740 DMIPS with three cores).<ref name="ref19484776952">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref><ref name="ref2022357806">UDE Debug, Trace and Test solutions for Infineon TriCore™ AURIX™ TC32, TC33, TC35, TC36, TC37, TC38, TC39, TC3x Microcontrollers https://www.pls-mc.com/products/infineon-tricore-aurix-tc32-tc33-tc35-tc36-tc37-tc38-tc39-microcontrollers/</ref><ref name="ref14281090103">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref>
===Memory Subsystem and Cache===
AURIX™ TC3xx microcontrollers integrate a large on-chip memory system to meet real-time and safety requirements. Program flash memory sizes range up to 16 MB on the largest models, with over 6 MB of on-chip SRAM available for data and scratchpad usage. Each TriCore CPU has its own tightly-coupled local memories as well as caches: for example, each core includes a 32 KB instruction cache and a 16 KB data cache. In addition, every core has separate local RAM blocks (Harvard architecture) for instructions and data (often termed PSPR and DSPR – Program Scratch-Pad RAM and Data Scratch-Pad RAM) that allow deterministic access for time-critical routines. Shared global memory is provided via a Local Memory Unit (LMU) which can be up to several hundred kilobytes (for instance, 768 KB in the TC39x) accessible by all cores. The memory system is connected by a high-bandwidth internal bus fabric (the SRI crossbar and peripheral buses) that arbitrates access between cores, DMA engines, and peripherals. This architecture ensures that each core can quickly fetch instructions and data either from its local cache/RAM or the central memory, enabling efficient parallel processing. Memory protection hardware is also built-in to isolate tasks of different criticality, an important feature for safety and security.<ref name="ref19484776952" /><ref name="ref5727814512">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
===Peripherals and Interfaces===
One of the strengths of the AURIX™ TC3xx architecture is its extensive set of on-chip peripherals and interface controllers, designed to handle the complex networking and I/O needs of modern vehicles and industrial systems. Key peripheral features and interfaces include:<ref name="ref19484776952" /><ref name="ref2022357806" /><ref name="ref14281090103" /><ref name="ref3635926">AURIX Training System Architecture https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_System_Architecture-Training-v01_00-EN.pdf?fileId=5546d46272e49d2a0172eb476d56739e</ref>

* '''Networking Interfaces:''' Multiple CAN FD controllers (supporting up to 12 CAN-FD channels in high-end variants) for in-vehicle networking, with legacy CAN and LIN interfaces (up to 24 LIN channels) for lower-speed device communication. Many TC3xx devices also integrate up to two FlexRay controllers for time-triggered automotive networks (maintaining compatibility with earlier automotive communication standards). For high-bandwidth data, a Gigabit Ethernet MAC is included, enabling uses like automotive Ethernet (e.g., audio-video bridging and IP-based connectivity).
* '''Analog and Timers:''' A suite of analog peripherals including multiple ADC units for sensor interfacing and motor control, and DACs in some models. Sophisticated timer units are on-chip, notably the Generic Timer Module (GTM) and Capture/Compare Units (CCU6), which can generate complex PWM waveforms and handle events for engine control, power inverters, or robotics with minimal CPU intervention. These timers enable precise control of actuators (e.g. fuel injection timing, electric motor commutation) in real time.
*'''Serial Interfaces:''' SPI, I²C, UART/LIN and other serial interfaces for connecting to external sensors, actuator controllers, and memory. The controllers often support multiple instances (several SPI channels, etc.) to accommodate numerous devices. AURIX™ TC3xx also provides an external bus interface (EBU) for parallel memory or FPGA connectivity, and an SD/MMC interface (eMMC) to connect external flash memory for data logging or over-the-air update storage.
*'''Dedicated Processing Units:''' Some AURIX™ TC3xx models include special accelerators, such as a hardware Fast Fourier Transform unit (HW-FFT) and up to two Signal Processing Units (SPUs) optimized for radar signal processing. These enable the microcontroller to handle radar front-end data or other intensive DSP tasks (like Fourier transforms for radar or audio signals) on-chip, which is crucial for advanced driver assistance sensors. There is also a ''Security Module'' (covered in a later section) and a Safety Management Unit that supervise system integrity.
*'''Other On-chip Modules:''' Watchdog timers, error-correction coders for memories (ECC on flash and RAM for reliability), a programmable interrupt system, multiple DMA channels (up to 128 DMA channels) for efficient data movement, and debug interfaces (JTAG and a 2/3-pin DAP) for development. The on-chip debug system supports tracing of program execution (via a built-in Emulation Memory, MCDS) to aid in complex multicore software development.

Overall, the AURIX™TC3xx provides a highly integrated SoC-like platform, allowing a single chip to manage tasks ranging from powertrain control and chassis control to infotainment gateways. This high level of integration reduces the need for separate companion chips and helps to lower system complexity and cost.
===Performance and Benchmarking===
Fabricated in a 40 nm embedded flash process<ref name="ref2022357806" />, AURIX™ TC3xx processors achieve significant performance gains over prior generations while maintaining automotive-grade power efficiency. With six 32-bit cores at 300 MHz (four of them paired in lockstep), a flagship TC3xx device (e.g., TC39x) can deliver up to approximately 2,400 DMIPS of aggregate computing throughput<ref name="ref2022357806" />. In terms of per-core performance, the TriCore architecture yields around 1.3–2.0 DMIPS/MHz depending on the instruction mix, meaning each 300 MHz core can approach ~400–600 DMIPS in optimized scenarios<ref name="ref14281090103" /><ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. This is on par with or exceeding many contemporary 32-bit automotive MCUs. The integrated DSP extensions and optional accelerators (like the FFT unit) also enable high-speed signal processing, with Infineon citing up to ~1.8 GFLOPS of DSP throughput for certain operations<ref name="ref1222155140" />.

Real-world performance improvements of the TC3xx over its predecessor are notable: for example, compared to the first-generation AURIX™ (which offered up to 740 DMIPS), the TC3xx’s expanded core count and clock speed provide roughly three times the computational power on the same type of workload<ref name="ref14281090103" />. This extra headroom allows more functions (such as running multiple control algorithms or sensor fusion tasks in parallel) to be consolidated onto one microcontroller without compromising real-time deadlines<ref name="ref14281090103" />. Despite the increase in speed and core count, the TC3xx family was designed with power and thermal constraints in mind, achieving these gains within similar power consumption envelopes as the previous generation by leveraging the smaller 40 nm process and power-saving features like clock gating<ref name="ref5727814512" />. The deterministic real-time performance (with features like lockstep and tightly-coupled memory) makes the AURIX™ TC3xx suitable for the most demanding automotive applications, where consistent low latency and high throughput are required simultaneously.

== On-Chip System Connectivity and Bridges ==
[[File:TC3xx On-Chip System Connectivity.png|thumb|The TC3xx has two '''SRI Domains''' (SRI0 and SRI1). CPU0 to CPU3 are connected to SRI0, CPU4/5 are connected to SRI1.|alt=TC3xx On-Chip System Connectivity|423x423px]]
The AURIX™ TC3xx Platform has three independent on-chip connectivity resources:

* '''System Resource Interconnect Fabric (SRI Fabric)''' connects the TriCore CPUs, the DMA module, and other high bandwidth requestors to high bandwidth memories and other resources for instruction fetches and data accesses. A key component of the fabric is the SRI crossbar, which connects all the agents in one SRI domain. The SRI crossbar carries the transactions between the SRI Masters and SRI Slaves of the domain. The SRI crossbar supports parallel transactions between different SRI Master and SRI Slave agents. In addition to the parallelism of concurrent requests, it also supports pipelined requests from an SRI Master to a SRI Slave.
* '''System Peripheral Bus (SPB)''' connects the TriCore CPUs, the DMA module, and other SPB masters to the medium and low bandwidth peripherals. SPB masters do not directly connect to the SRI Fabric, and will access SRI attached resources via a SFI_F2S Bridge.
* '''Back Bone Bus (BBB)''' connects the TriCore CPUs, the DMA module, and SPB masters with ADAS resources. SRI Masters do not directly connect to the BBB, but access BBB attached resources via a SFI_S2F Bridge. SPB masters also do not directly connect to the BBB, but access BBB attached resources via bridging over the SRI Fabric.

=== CPU Resource Access Times ===
These tables describe the CPU access times to various resources in CPU clock cycles for the AURIX™ TC3xx Platform. In the case of load or fetch accesses, the access times are the minimum number of CPU stall cycles to complete the access. If there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

For write access, the access times are the maximum for a sequence of such access (non-conflicting). In many cases for a singleton access, or a short sequence, write buffering reduces the stall effect seen by a CPU, sometimes to 0. However, as with loads and fetches, if there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

==== Access latency for global resources ====
{| class="wikitable"
|+
! CPU Access Type !! CPU stall cycles
!Notes
|-
| Data read from System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
| rowspan="2" |The final number of stall cycles will depend on the real number of WS generated by the target resource.
|-
| Data write to System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC39x, TC37xED) || <math>9 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
| rowspan="2" |When SFI_S2F is connected to XBar2 (TC39x and TC37xED) there is an additional latency due to access going through an S2S.
|-
| Data write to Back Bone Bus (BBB) (TC39x, TC37xED) || <math>5 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC35x, TC33xED) || <math>6 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
|
|-
| Data write to Back Bone Bus (BBB) (TC35x, TC33xED) || <math>3 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|
|}


* '''Module Wait State''': The number of wait states for read and for write accesses is >= 1 and depends on the accessed module and its configuration.


==== CPU Accesses: Stall cycles for local and SRI resources ====
{| class="wikitable"
|+
! CPU Access Type !! Local CPU !! Local SRI !! Remote SRI Domain
|-
| Data read from DSPR || 0 || 7 || 10
|-
| Data write to DSPR || 0 || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from DSPR || See local SRI column || 7 || 10
|-
| Data read from DLMU || 0 || 7 || 10
|-
| Data write to DLMU || 2 || 5, {{rev|3|with Pipelining}}|| 5, 4
|-
| Instruction fetch from DLMU || See local SRI column || 7 || 10
|-
| Data read from PSPR || See local SRI column || 7 || 10
|-
| Data write to PSPR || See local SRI column || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from PSPR || 0 || 7 || 10
|-
| Data read from PFlash || 5 + PWS || 10 + PWS || 13 + PWS
|-
| Instruction fetch from PFlash (buffer miss) || 2 + PWS || 9 + PWS || 12 + PWS
|-
| Instruction fetch from PFlash (buffer hit) || 3 || 6 || 9
|-
| Data read from LMU || n.a. || 7 || 10
|-
| Data write to LMU || n.a. || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from LMU || n.a. || 7 || 10
|-
| Data read from DFlash || n.a. || 5 + 3*(3 + DCWS) || 8 + 3*(3 + DCWS)
|-
| Data read access from EMEM (TC39x, TC37xED) || n.a. || n.a. || 14, {{rev|15|fBBB < fSRI}}
|-
| Data write access to EMEM (TC39x, TC37xED) || n.a. || n.a. || 9
|-
| Data read access from EMEM (TC35x, TC33xED) || n.a. || 11, {{rev|12|fBBB < fSRI}}|| n.a.
|-
| Data write access to EMEM (TC35x, TC33xED) || n.a. || 9 || n.a.
|-
| Data read access from DAM || n.a. || 10 || 13
|-
| Data write access to DAM || n.a. || 7 || 7
|}

* '''Remote SRI Domain''': Only applies to products with SRI extenders. Additional latency due to access going through an S2S
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''DCWS''': Configured DFlash Corrected Wait States (Includes cycles for DFlash access cycles and ECC correction latency)

== CPU Subsystem ==
[[File:TC3xx Processor Core, Local Memory and Connectivity.png|alt=TC3xx Processor Core, Local Memory and Connectivity|thumb|Processor Core, Local Memory and Connectivity]]The Infineon AURIX™ TC3xx features up to 6 processor cores (CPU0 ... CPU5) implementing the [[TriCore Instruction Set Architecture|TC1.6.2 instruction set architecture]]. The following section focuses on the microarchitectural details of the CPU subsystem. For more information about the ISA, please take a look at the [[TriCore Instruction Set Architecture]].

The processor core connects to the following memories and bus interfaces (where implemented):
*Program Scratch-Pad SRAM (PSPR)
*Data Scratch-Pad SRAM (DSPR)
*Program Cache (PCache)
*Data Cache (DCache)
*Local Memory Unit (DLMU)
*Local Pflash bank (LPB)
*SRI slave interface (x2)
*SRI master Interface
*SPB master interface

=== TC1.6.2P Implementation Features ===
*Most instructions executed in 1 cycle
*Branch instructions in 1, 2 or 3 cycles (using dynamic branch prediction)
*Wide memory interface for fast context switch
* Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
*Six memory protection register sets
*Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
*Third pipeline for loop instruction only (zero overhead loop)
*Single precision Floating Point Unit (IEEE-754 Compatible)
*Dedicated Integer divide unit
*18 data memory protection ranges, 10 code memory protection ranges arranged in 6 sets

=== Superscalar Architecture ===
The processor core within the AURIX™ TC3xx family, specifically the TC1.6.2P implementation, employs a superscalar architecture characterized by three parallel pipelines: the Integer Pipeline, the Load/Store Pipeline, and the Loop Pipeline. Superscalar execution is a form of instruction-level parallelism that enables the processor to issue and execute multiple instructions during a single clock cycle. The TriCore TC3xx core's superscalar architecture allows it to issue and execute multiple instructions in parallel. Specifically, it can issue up to two instructions simultaneously to the Integer and Load/Store pipelines. However, there are certain constraints on this dual issuing capability. For example, back-to-back data arithmetic instructions can only be issued in separate cycles, and a load/store instruction can be issued either on its own or paired with a data arithmetic instruction, provided the load/store instruction is the second in the pair. Under ideal conditions, with careful instruction scheduling, this dual-issue capability can lead to a throughput of close to 0.5 clock cycles per instruction, effectively executing two instructions per cycle.

=== Pipeline Stages ===
The execution of instructions within the TriCore TC3xx core is managed through a pipeline consisting of several stages. In one document it is mentioned that the pipeline consists of 6 stages <ref name="ref3635926" />, but the exact stages remain unclear. From the architecture the following stages can be inferred:

* '''Fetch Stage''': The initial stage in the pipeline is the Fetch stage, where instructions are retrieved from memory. This task is handled by the Instruction Fetch Unit (IFU), which is responsible for fetching instructions from the memory system. To improve efficiency, the IFU employs a pre-fetching mechanism, anticipating the instructions that will be needed and bringing them into the processor before they are actually required. Instructions are fetched through a 64-bit wide Program Memory Interface (PMI), allowing for the retrieval of a significant amount of instruction data in each cycle. The fetched instructions are then placed into an issue FIFO, a buffer capable of holding up to six instructions. This buffer plays a crucial role in managing the flow of instructions to the subsequent execution pipelines. The 64-bit fetch width and the instruction buffer are indicative of a design that aims to ensure a continuous supply of instructions to the pipelines, preventing them from being starved of work. A wider fetch path allows for more instruction bits to be obtained from memory in each clock cycle, while the buffer helps to mitigate temporary delays in instruction fetching.
* '''Execution Unit''': The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop Pipeline. All three pipelines operate in parallel and are capable of executing instructions simultaneously. Each pipline has its own decode stage and two execute stages. Furthermore, the TC3xx features a Floating Point Unit (FPU). It is not clear whether the FPU is part of the execution unit or a separate unit. It is assumed that the FPU also has its own decode stage and an unknown number of execute stages
** '''Decode Stage''': Following the Fetch stage, the instruction are issued to one of the pipelines. In the decode stage of each pipeline, the instruction is examined and translated to determine the specific operation it represents and to identify the operands it will operate on. It is assumed that operands are read from the register file during the decode stage.
** '''Execute Stage''': The Execute stage is where the actual operation specified by the instruction is carried out. Pipeline hazards (stalls) are minimised by the use of forwarding paths between pipeline stages allowing the results of one instruction to be used by a following instruction as soon as the result becomes available.
** '''Writeback Stage''': The final stage in the pipeline is the Writeback stage. In this stage, the results produced by the executed instruction are written back to the processor's register file, making them available for subsequent instructions. It is unclear whether the writeback stage is part of the (two) execution stages or a separate stage.

=== Execution Pipelines ===
The TriCore TC3xx core leverages four parallel pipelines to enhance its performance. Each pipeline is designed to handle a specific class of instructions:

* '''Integer Pipeline:''' This pipeline is responsible for executing integer arithmetic and logical instructions, including data-conditional jump instructions, bit manipulation operations, as well as division and multiply-accumulate (MAC) instructions.
* '''Load/Store Pipeline:''' The primary function of this pipeline is to manage memory access operations, including loading data from memory and storing data to memory. It also handles address arithmetic, unconditional jump instructions, procedure call instructions, context-switching operations, and control flow related to context save areas (CSAs).
* '''Loop Pipeline:''' This is a specialized pipeline designed to facilitate zero-overhead loops, a technique that significantly improves the performance of iterative code sections. Its design aims to eliminate or minimize the overhead typically associated with loop control, such as incrementing counters and checking loop conditions. Some documentation suggests that the loop pipeline comes along with a "Loop Cache". This dedicated cache would likely be used to store instructions belonging to the loop, enabling very fast access and execution for repeated iterations.
* '''Floating Point Unit (FPU):''' The FPU is responsible for executing floating-point arithmetic operations

=== Store Buffers ===
The TriCore TC3xx core include '''Store Buffers''' to decouple memory write operations from CPU instruction execution. All stores from the Load/Store Pipeline are placed in the store buffer prior to being written to local memory or transferred via the bus system. Write data is taken from the store buffers and written to memory when the target memory or bus interface becomes available. In normal operation the CPU will prioritise memory load operations over store operations in order to improve performance unless the store buffer is full or the order of load and store operations must be preserved (e.g. peripheral space access). The store buffer can hold the data for up to 6 stores operations. To improve performance the store buffer will merge consecutive byte, half-word, and word writes of the same location to reduce the number of memory accesses required.

=== Instruction Timing ===

==Functional Safety and Security Features==
===Hardware Security Module and Encryption===
One of the defining features of the AURIX™ TC3xx family is its robust hardware-based security subsystem, implemented to protect against cyber threats and unauthorized manipulation of vehicle systems. Each TC3xx MCU includes a dedicated ''Hardware Security Module'' (HSM), which is essentially an on-chip co-processor with its own CPU and cryptographic engine designed to handle secure operations. In the second-generation AURIX™ (TC3xx), the HSM was upgraded with support for asymmetric cryptography (e.g., RSA, ECC algorithms) in hardware, providing significantly faster public-key encryption and authentication capabilities than pure software implementations. This HSM supports '''EVITA Full''' (the highest level of the EU’s EVITA automotive security requirements), meaning it can perform secure boot, message authentication, and encryption at a level suitable for protecting critical in-vehicle communications. For example, the HSM can encrypt and authenticate CAN/Ethernet messages to prevent spoofing or tampering on the vehicle network, and it can manage cryptographic keys securely isolated from the main application cores.<ref name="ref14281090104">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref2022357806" />

The security module enables features like '''secure boot''', where the AURIX™ will only execute firmware that is digitally signed by the vehicle manufacturer, thereby preventing unauthorized or malicious code. It also facilitates ''over-the-air (OTA) updates'' in a secure manner: the TC3xx HSM can verify and decrypt update packages received via telematics, allowing firmware upgrades while protecting against attackers attempting to hijack the software. In addition, the HSM includes a true random number generator and supports protocols for immobilizer and theft protection systems. Infineon’s implementation essentially treats the HSM as an “embedded smart card” inside the microcontroller. This approach, building on Infineon’s expertise in chip card security, helps to safeguard sensitive assets like cryptographic keys and to perform secure operations (encryption, decryption, authentication) in hardware, making attacks significantly more difficult. The strong cybersecurity provisions of the AURIX™ TC3xx have made it a preferred choice for vehicle gateway ECUs and central body controllers, which are points of entry for connected car communications and thus high-value targets for hackers. By incorporating the HSM, automotive OEMs can implement advanced security features such as encrypted onboard communication (to thwart bus tampering) and secure diagnostics, ensuring the vehicle’s electronic data is protected against cyber threats even as cars become more connected.<ref name="ref14281090104" /><ref name="ref5727814513">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref><ref name="ref19484776953">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
=== Functional Safety and Fault Tolerance===
Beyond cybersecurity, the AURIX™ TC3xx architecture is built with extensive ''functional safety'' features to meet the highest safety integrity levels in automotive systems. The multi-core design supports ''lockstep operation'', where redundant checker cores run in parallel with main cores and continuously compare results cycle-by-cycle. In TC3xx devices, up to four of the six TriCore CPUs have such lockstep partner cores, allowing the microcontroller to detect any single-point CPU failure instantly (if a discrepancy arises between the core and its checker, a fault is signaled). A ''Safety Management Unit (SMU)'' is integrated on-chip to monitor various fault conditions throughout the device – it aggregates error signals from the lockstep cores, memory ECC monitors, clock/watchdog monitors, and peripheral self-tests, and can initiate safe-state actions (like resetting the chip or signaling an error pin to an external supervisor) if a critical fault is detected. The AURIX™ safety concept also includes a distributed Memory Protection Unit (MPU) arrangement, with multiple memory protection contexts that prevent errant or malicious code from writing to wrong memory areas. This helps contain faults and eases the integration of software with mixed criticality (Infineon allows partitioning software components of different ASIL levels on the same MCU while keeping them isolated).<ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref19519075552">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref>

Crucially, the TC3xx family was developed according to ISO 26262 processes and can achieve '''ASIL-D''' (Automotive Safety Integrity Level D), the highest grade for automotive functional safety. Compared to a traditional dual-core lockstep approach, the AURIX’s™ multi-core safety architecture allowed Infineon to reduce certain safety development overheads (earlier Infineon data suggested up to 30% reduction in safety software workload) by providing built-in safety mechanisms and diagnostics. Infineon supplies a comprehensive safety manual and diagnostic libraries for the AURIX™, helping engineers utilize features like CPU self-tests, RAM tests, and CRC checks to comply with safety standards. In addition to automotive standards, the AURIX™ TC3xx has also been qualified for '''industrial safety''': in 2023, Infineon announced support for IEC 61508 metrics, enabling designs with AURIX™ to reach SIL-2 and SIL-3 safety integrity levels for industrial applications. This cross-industry safety compliance is facilitated by the MCU’s redundant design and detailed failure mode documentation (FMEDA) provided by Infineon. In summary, the AURIX™ TC3xx integrates both proactive safety (fault prevention via lockstep, monitoring and protection) and reactive safety (fault detection and safe shutdown), making it a dependable component for systems that cannot afford unintended behavior, whether in cars, factories, or aerospace. <ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref4967712052">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref><ref name="ref196858272">MCUs support industrial functional safety - Electronic Products https://www.electronicproducts.com/mcus-support-industrial-functional-safety/</ref>
== Platform Devices ==
The following table shows a feature overview of the AURIX™ TC3xx Platform family focusing on memory and number of cores.
{| class="wikitable"
!
!Feature
!TC33x
!TC33xEXT
!TC35x
!TC36x
!TC37x
!TC37xEXT
!TC38x
!TC39x
|-
| rowspan="2" |CPUs
|Cores / Checker Cores
|1 / 1
|2 / 1
|3 / 2
|2 / 2
|3 / 2
|3 / 3
|4 / 2
|6 / 4
|-
|Max. Freq.
| colspan="8" |300 MHz
|-
| rowspan="2" |Cache per CPU
|Program [KB]
| colspan="8" |32
|-
|Data [KB]
| colspan="8" |16
|-
| rowspan="3" |SRAM per CPU
|PSPR [KB]
|8
|{{rev|32|CPU0}}
{{rev|64|other}}
|64
|32
|64
|64
|64
|64
|-
|DSPR [KB]
|192
|{{rev|192|CPU0}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|192
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|-
|DLMU [KB]
|8
|{{rev|8|CPU0}}
{{rev|64|other}}
|64
|64
|64
|64
|64
|64
|-
| rowspan="2" |SRAM global
|LMU [KB]
| -
| -
|512
| -
| -
| -
|128
|768
|-
|DAM [KB]
| -
| -
|32
| -
|64
|64
|128
|128
|-
| rowspan="3" |Extension Memory (EMEM)
|TCM [MB]
| -
|1
|2
| -
| -
|2
| -
|2
|-
|XCM [MB]
| -
| -
| -
| -
| -
|1
| -
|2
|-
|XTM [KB]
| -
|16
|16
| -
| -
|16
| -
|16
|-
| rowspan="2" |Program Flash
|Size [MB]
|2
|4
|4
|4
|6
|10
|10
|16
|-
|Banks [MB]
|1 x 2
|2 x 2
|2 x 2
|2 x 2
|2 x 3
|3 x 3, 1 x 1
|3 x 3, 1 x 1
|5 x 3, 1 x 1
|-
| rowspan="2" |Data Flash
|DF0 Size (single-ended) [KB]
|128
|128
|128
|128
|256
|512
|512
|1024
|-
|DF1 Size (single-ended) [KB]
|128
|128
|128
|128
|128
|128
|128
|128
|-
| rowspan="3" |DMA
|Channels
|64
|64
|64
|64
|128
|128
|128
|128
|-
|Move Engines
|2
|2
|2
|2
|2
|2
|2
|2
|-
|Resource Partitions
|4
|4
|4
|4
|4
|4
|4
|4
|}

== Compilers ==
The AURIX™ TC3xx family is a series of high-performance microcontrollers widely used in automotive and industrial applications. Compilers for the AURIX™ TC3xx are crucial for developers aiming to optimize performance, reliability, and safety in their applications. One significant aspect of the compiler landscape for AURIX™ TC3xx is the limited direct support from mainline open-source compilers such as GCC or LLVM/Clang. The primary reason for this is the stringent requirements for functional safety in automotive and industrial applications, which demand specialized features and compliance with safety standards that are often not met by general-purpose open-source compilers.

=== Commercial Compilers ===

# '''Tasking''': Tasking compilers are renowned for their robust support for automotive applications, offering advanced debugging capabilities and optimization techniques tailored for the AURIX™ architecture. They provide extensive code optimization, comprehensive debugging tools, and strong support for safety standards such as ISO 26262, making them ideal for developing high-performance, reliable, and safe applications.
# '''HighTec''': The HighTec compiler is a popular choice, known for its Eclipse-based development environment and strong multicore support. HighTec provides both GCC and LLVM-based ports of open-source compilers tailored specifically for the AURIX™ TC3xx family. These compilers offer efficient parallel execution, advanced code analysis, and an integrated development environment, ensuring robust performance and compliance with safety standards.
# '''Green Hills Software''': Green Hills Software provides a highly optimized toolchain aimed at safety-critical applications, focusing on high performance and strict compliance with automotive standards. Their compiler offers superior optimization, extensive safety features, and a proprietary IDE with specialized tools for automotive development, ensuring developers can meet the stringent demands of functional safety.

=== GCC for AURIX™ ===

While mainline GCC does not directly support the AURIX™ TC3xx family, there is an unofficial GCC version available for AURIX™. Due to the GNU General Public License (GPL), the source code from HighTec was retrieved and, along with binary versions, published on GitHub:

*GCC 4.9.4/Binutils 2.20/Newlib 1.18 for Tricore AURIX™ [[https://github.com/volumit/package_494 Source]] [[https://github.com/volumit/tricore_gcc494_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc494_linux_bins Prebuild Linux Binaries]]
*GCC 9.4.0/Binutils 2.20/Newlib 1.18 for Tricore AURIX™ [[https://github.com/volumit/package_940 Source]] [[https://github.com/volumit/tricore_gcc940_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc940_linux_bins Prebuild Linux Binaries]]
*GDB 10.0.50 for Tricore AURIX™ [[https://github.com/volumit/gdb-tricore Source]]
==emmtrix Tools for AURIX™ TC3xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX™ TC3xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

==See Also==

*[[Infineon AURIX TC4x|Infineon AURIX™ TC4x]]
*[[Infineon AURIX TC2xx|Infineon AURIX™ TC2xx]]
*[[TriCore Instruction Set Architecture]]

==External Links==

*https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/
*[https://documentation.infineon.com/aurixtc3xx/docs/qmd1702366622648 AURIX™ TC3xx user manuals]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d3605221d96 AURIX™ TC3xx User Manual Part-1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d35f8541d94 AURIX™ TC3xx User Manual Part-2]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd AURIX™ TC3xx Architecture vol 1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 AURIX™ TC3xx Architecture vol 2]

== References ==
<references />
[[Category:Supported Architectures]]

{{#seo:
|title=Infineon AURIX TC3xx Family – Deep Dive
|description=This deep dive into Infineon's AURIX TC3xx family explores its multi-core TriCore architecture, real-time capabilities, safety and security features and tools
|image=File:AURIX_TC399_LFBGA-516_plain.jpg
|keywords=AURIX, Infineon, TC3xx, microcontroller, TriCore, automotive, ADAS, ISO 26262, functional safety, embedded security, ASIL-D, deep dive
}}

Infineon AURIX TC2xx

2025-04-08T07:21:05Z

Mira.steinmetz:

'''Infineon AURIX™ TC2xx''' is a family of 32-bit automotive microcontrollers developed by Infineon Technologies. ''AURIX™'' stands for ''“Automotive Realtime Integrated Next Generation Architecture”'', reflecting its design for real-time, safety-critical automotive applications<ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. The TC2xx series (first-generation AURIX™) is based on a multicore architecture featuring up to three independent 32-bit '''TriCore''' processor cores. Introduced around 2012, the AURIX™ TC2xx marked Infineon’s transition to a multicore microcontroller platform (fabricated in 65 nm technology) after earlier single-core TriCore generations. It was designed from the ground up to meet stringent automotive safety requirements (ISO 26262) and to provide higher performance and integration for applications like engine management, chassis control, and driver assistance systems.<ref name="ref1222155140" /><ref name="ref1490396573">Optimized for Success - EE Times Europe https://www.eetimes.eu/optimized-for-success/</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>

The AURIX™ TC2xx family’s design philosophy is to combine '''safety''', '''security''', and '''performance''' in one scalable MCU platform. It achieves high functional safety compliance (up to '''ASIL-D''', the highest automotive safety integrity level) with less development effort compared to traditional dual-controller lockstep systems<ref name="ref572781451" />. Infineon claims that using AURIX™ can cut safety-related development time by ~30% versus classical lockstep architectures, thanks to its built-in fault detection and monitoring hardware. At the same time, the TC2xx provides significant performance headroom – roughly 50% to 100% higher computational performance compared to its predecessors – while maintaining power consumption similar to previous single-core designs. To address emerging automotive security needs, the AURIX™ MCUs also integrate a dedicated Hardware Security Module ('''HSM''') on-chip, which protects against IP theft, fraud, and tampering. This combination of features makes the AURIX™ TC2xx a popular choice for consolidating various automotive control functions (powertrain, safety, body, etc.) onto one platform, without sacrificing reliability or efficiency.<ref name="ref572781451" /><ref name="ref71179009">32-bit TriCore™ AURIX™– TC2xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/</ref>
==Architecture==
The AURIX™ TC2xx is built on Infineon’s '''TriCore''' architecture, which uniquely unifies traits of a RISC processor, a microcontroller, and a DSP (digital signal processor) into one core design. Each TriCore CPU in the TC2xx is a 32-bit superscalar processor that supports both 32-bit and 16-bit instruction formats (the latter for code size efficiency). The TriCore instruction set architecture includes typical RISC features (load/store architecture, 4 GB address space) and DSP capabilities (such as multiply-accumulate instructions and bit manipulation) in a single core. The cores also have an optional floating-point unit (FPU) and support SIMD (single-instruction multiple-data) operations for signal processing acceleration. The maximum core frequency in the TC2xx family is 300 MHz, and devices achieve about 1.7–2.4 DMIPS/MHz per core, providing robust real-time performance.<ref name="ref1222155140" /><ref name="ref71179009" />

In terms of core configuration, high-end AURIX™ TC2xx models implement three main TriCore CPUs, which can be run in parallel or in redundant (lockstep) pairs for safety. Some variants include a redundant checker core that shadows a primary core to detect calculation errors (a technique to meet SIL/ASIL safety goals). The multicore architecture is supported by a layered memory system: each TriCore has tightly coupled local memory for fast instruction and data access, and they share access to large on-chip Flash and RAM via an internal bus matrix. Memory options in the TC2xx range from about '''0.5 MB up to 8 MB of on-chip Flash''', and from ~50 KB up to 2.7 MB of SRAM, depending on the specific device. This on-chip memory (with ECC protection on memories for safety) allows real-time code execution and data storage without external memory in most use cases. For peripherals and I/O, the AURIX™ architecture includes a rich set of on-chip modules connected via internal buses, such as analog-to-digital converters, timer units, communication interfaces, and direct memory access (DMA) controllers. AURIX™ TC2xx MCUs typically provide interfaces like multiple CAN/CAN-FD channels, LIN/UART, SPI, I²C, Ethernet (on higher-end models), and automotive-specific buses (e.g. FlexRay on some variants), making the chip a self-contained controller for complex automotive networks.'''<ref name="ref572781451" />'''<ref name="ref71179009" /><ref name="ref957370148">Infineon TriCore - Wikipedia https://en.wikipedia.org/wiki/Infineon_TriCore</ref>

The '''Generic Timer Module (GTM)''' is a notable part of the AURIX™ TC2xx architecture. It is a sophisticated timer/co-processor integrated on-chip to handle complex timing, PWM generation, input capture, and other signal conditioning tasks across more than 200 channels. There are also specialized accelerators and co-processors on certain TC2xx devices, such as a '''Hardware Fast Fourier Transform (HFFT)''' unit for signal processing and a '''Parallel Pixel Processor''' for simple video or sensor data processing. These dedicated engines offload the TriCore CPUs for specific high-load tasks (e.g. radar signal FFTs or encoder signal processing), improving overall throughput in automotive applications. The AURIX™ architecture uses a single-power supply (5V or 3.3V) design and includes an on-chip voltage regulator (EVR), simplifying power management. The MCUs are offered in a variety of package types (from compact QFP-64 up to large BGA-516) to accommodate different I/O needs. Overall, the TC2xx architecture is highly integrated and optimized for real-time, combining multiple CPU cores with ample flash memory, SRAM, and peripherals on one chip to serve as a '''central control unit''' in vehicles.<ref name="ref1222155140" /><ref>Aurix Unleashed - RS Components https://docs.rs-online.com/0f3f/0900766b815c315c.pdf</ref>
====CPU access latency (TC29x) ====
{| class="wikitable"
!CPU Access Type!!Local CPU
|-
|Data read access to own DSPR||0
|-
|Data write access to own DSPR||0
|-
|Data read access to own or other PSPR||8
|-
|Data write access to own or other PSPR||0
|-
|Data read access to other DSPR||8
|-
|Data write access to other DSPR||0
|-
|Instruction fetch from own PSPR
|0
|-
|Instruction fetch from other PSPR (critical word)||8
|-
|Instruction fetch from other PSPR (any remaining words)||0
|-
|Instruction fetch from other DSPR (critical word)||8
|-
|Instruction fetch from other DSPR (any remaining words)||0
|-
|Initial Pflash Access (critical word)||7 + configured PFlash Wait States
|-
|Initial Pflash Access (remaining words)||0
|-
|PMU PFlash Buffer Hit (critical word)||6
|-
|PMU PFlash Buffer Hit (remaining words)||0
|-
|Initial Dflash Access||7 + configured DFlash Wait States
|-
|TC1.6P Data read from System Peripheral Bus (SPB)
|{{rev|4|2=fCPU = fSPB}} {{rev|7|2=fCPU = 2*fSPB}} {{rev|10|2=fCPU = 3*fSPB}}
|-
|TC1.6P Data write to System Peripheral Bus (SPB)||0
|}
*

==Key Features==

* '''Safety Mechanisms:''' The AURIX™ TC2xx was developed via an ISO 26262-compliant process and includes multiple hardware mechanisms to achieve '''functional safety up to ASIL-D'''. Notably, it supports ''lockstep'' operation, where one or two of the TriCore CPUs can run in redundant lockstep mode with another core to detect discrepancies (faults) cycle-by-cycle. A Safety Management Unit ('''SMU''') is built in to monitor critical system parameters and handle faults. The architecture employs memory protection units and safe internal communication buses to isolate and supervise different software domains. Other safety features include '''error-correcting code (ECC)''' on flash and RAM, redundant peripherals (for example, duplicated ADC channels), watchdog timers, clock and voltage monitors, and self-test routines. These features allow developers to more easily implement safety-critical functions and meet standards like IEC 61508 (SIL-3) or ISO 26262 (ASIL-D) using a single AURIX™ MCU, whereas achieving the same on a traditional single-core MCU might require additional external safety ICs or companion processors.<ref name="ref1490396573" /><ref name="ref572781451" />
* '''Security Functions:''' Infineon integrated a dedicated Hardware Security Module ('''HSM''') into the AURIX™ TC2xx family to address automotive cybersecurity requirements. This HSM is essentially an on-chip co-processor (with its own CPU and flash) that handles cryptographic operations and secure key storage isolated from the main cores. It follows the EVITA (E-safety Vehicle Intrusion Protected Applications) guidelines for automotive security. The HSM enables features like secure boot, encryption/decryption, authentication, and detection of software tampering. By having a built-in “embedded smart card” for security, the AURIX™ can implement anti-theft, anti-cloning, and secure onboard communication measures without needing an external security chip. This integration is a key differentiator, as it helps protect vehicle functions (e.g. immobilizers, firmware updates, V2X communication) against hacking and unauthorized modifications.<ref name="ref1222155140" /><ref name="ref71179009" />
* '''Performance and DSP Capability:''' Each TriCore CPU in the TC2xx is capable of up to 300 MHz operation, and combined the multicore setup offers considerable processing power for an MCU (Infineon cites up to ~1.8 GFLOPS of DSP throughput for the highest models). The TriCore design delivers around '''1.7–2.4 DMIPS/MHz''' per core, meaning a triple-core AURIX™ at max frequency can exceed 2000 DMIPS of total throughput. The inclusion of DSP instructions and dedicated accelerators enables the AURIX™ to handle computationally intensive tasks (like control algorithms, filtering operations, or even rudimentary neural networks) that previously might require a separate DSP or FPGA. A built-in '''Floating Point Unit''' on each core supports single-precision (and optional double-precision in some cases) arithmetic, beneficial for model-based control algorithms and automotive sensor processing. Peripherals like the '''Generic Timer Module (GTM)''' and '''Hardware FFT''' accelerator (available on select TC2xx variants) further boost real-time performance for handling high-frequency events (e.g. engine ignition timing, motor control PWM, radar signal analysis) without overloading the CPU. Despite the performance, the TC2xx was designed with efficiency in mind; Infineon managed to double the performance over the prior generation (TC1xx AUDO) while keeping power consumption at comparable levels. The MCUs also support various low-power modes and a standby controller to minimize energy usage when parts of the system are idle.<ref name="ref1222155140" /><ref name="ref572781451" />
* '''Power and Integration:''' As a system-on-chip for vehicles, AURIX™ TC2xx integrates a wide range of '''communication interfaces''' and analog/digital peripherals. Common features include multiple CAN bus controllers (often with CAN FD support), LIN/UART, SPI and I²C channels, FlexRay communication in high-end models, and even Ethernet (in variants aimed at gateway or ADAS roles). High-resolution '''ADC units''' (with shared and redundant channels) allow precise sensor measurements for engine or chassis control. There are also specialized modules like delta-sigma ADCs and SENT interfaces for automotive sensor inputs. This rich peripheral set reduces the need for external components, helping to lower the overall system Bill of Materials. The TC2xx devices operate over a broad temperature range (typically –40 °C to +150 °C), meeting the demands of under-the-hood automotive environments. They run from a single supply (with internal regulators), simplifying designs, and support both 5 V and 3.3 V systems for compatibility with a variety of sensors and actuators. Combined with its safety and security features, the AURIX’s™ high integration makes it a one-chip solution for many complex embedded applications.<ref name="ref1222155140" /><ref name="ref1490396573" /><ref name="ref71179009" /><ref name="ref957370148" />

==Applications==
The Infineon AURIX™ TC2xx family is primarily targeted at the '''automotive industry''', especially domains requiring high reliability and real-time control. Its initial use cases were in '''powertrain''' and engine management systems – for example, controlling combustion engines, managing fuel injection and ignition, and coordinating electric motor and battery systems in hybrid or electric vehicles. The multi-core AURIX™ can run multiple control algorithms in parallel (e.g. for an engine’s cylinders, transmission and motor inverter concurrently), which is valuable in modern electrified powertrains. Beyond engines, AURIX™ TC2xx MCUs are used in '''chassis and safety systems''': they can serve as the central controller for '''anti-lock braking systems (ABS)''' and stability control, '''airbag control units''', '''electric power steering (EPS)''' systems, and suspension controllers. Advanced Driver Assistance Systems ('''ADAS''') and autonomous driving modules in earlier generations of vehicles have also employed AURIX™ for tasks such as sensor fusion, radar signal processing, and acting as a safety supervisor for driving assistance features<ref name="ref572781451" />. For example, a radar unit for adaptive cruise control might use an AURIX™ to perform real-time signal processing (using its DSP capabilities and HFFT) and make high-level decisions, all within an ASIL-D safe environment.<ref name="ref572781451" /><ref name="ref1228701036">https://resources.tasking.com/sites/default/files/2021-02/Take%20Advantage%20of%20Infineon%20AURIX%20TC3xx%20Family%20With%20the%20Right%20Compiler_WEB.pdf</ref>

Thanks to its safety certification and robust design, the AURIX™ TC2xx has seen adoption in any application that cannot tolerate failure. This includes '''industrial automation and robotics''', where the MCU’s reliability and support for functional safety (IEC 61508) are attractive. In industrial motor drives or robotics controllers, an AURIX™ might handle precise motor control algorithms and system monitoring. Other use cases outside pure automotive include '''commercial vehicles and transportation''' (trucks, agricultural and construction machinery), which have similar safety and durability requirements. The AURIX’s™ extensive communication interfaces also make it suitable as a gateway or central node in complex networks – for instance, acting as a domain controller in modern automotive E/E architectures to coordinate data between powertrain, body, and ADAS subsystems. Some '''electric vehicle (EV)''' platforms use AURIX™ MCUs in battery management systems and inverter controls, leveraging its calculation power for battery algorithms and its safety for monitoring cell health. In summary, the TC2xx family finds use in scenarios that demand '''real-time performance with high safety integrity''', predominantly in automotive (engine, transmission, chassis, safety, ADAS) but also in high-end industrial embedded systems.<ref name="ref71179009" /><ref name="ref1228701036" />

==emmtrix Tools for AURIX™ TC2xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX™ TC2xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ TC2xx / [[Infineon AURIX TC3xx|TC3xx]]/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

== See Also ==

* [[Infineon AURIX TC3xx]]
* [[Infineon AURIX TC4x]]
* [[TriCore Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/
* [https://www.infineon.com/dgdl/Infineon-TC29x_B-step-UM-v01_03-EN.pdf?fileId=5546d46269bda8df0169ca1bdee424a2 TC29x B-Step User Manual]

== References ==
<references />
[[Category:Supported Architectures]]

Infineon AURIX TC3xx

2025-03-28T11:44:17Z

Mira.steinmetz:

[[File:AURIX TC399 LFBGA-516 plain.jpg|thumb|Infineon AURIX™ TC3xx second-generation microcontroller (TC399 BGA package). The AURIX TC3xx family integrates multiple TriCore CPUs and on-chip safety/security modules for automotive applications.|alt=TC399 BGA package]]
The '''Infineon AURIX TC3xx''' (Automotive Realtime Integrated neXt-generation architecture) is a family of 32-bit automotive microcontrollers introduced as the second generation of Infineon’s AURIX platform. Launched in 2016 as a successor to the earlier [[Infineon AURIX TC2xx|AURIX TC2xx series]], the TC3xx devices emphasize high performance, functional safety, and embedded security for advanced automotive and industrial applications. AURIX TC3xx microcontrollers feature a hexa-core [[TriCore Instruction Set Architecture|''TriCore'' processor architecture]] with enhanced safety measures, making them well-suited for demanding tasks such as autonomous driving domain controllers, powertrain control, and sensor data fusion in advanced driver-assistance systems (ADAS). The combination of multiple CPU cores, extensive on-chip memory, and a rich peripheral set allows TC3xx chips to deliver real-time responsiveness and reliability in safety-critical environments while meeting stringent automotive standards (such as ISO 26262 for functional safety).<ref name="ref1951907555">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref><ref name="ref1428109010">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref1948477695">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
==Applications==
AURIX TC3xx microcontrollers are used in a variety of safety-critical and high-performance applications across the automotive and industrial sectors. Key application domains include:
*'''Automotive Systems:''' The TC3xx family was primarily designed for automotive use and finds broad application in vehicles’ electronic control units (ECUs). Notably, it is used in ''powertrain and drivetrain control'' (engine management, transmission control, hybrid/electric vehicle inverter control, battery management) where its real-time processing and resilience support precise actuator control. It is also deployed in ''chassis and safety systems'' such as anti-lock braking systems (ABS), electronic stability control, airbag controllers, and electric power steering, leveraging its redundancy and fast response for fail-safe operation. With the growth of ADAS and autonomous driving, AURIX TC3xx devices serve as domain controllers for ''ADAS sensor fusion'', handling data from radar, LiDAR, camera, and ultrasonic sensors and performing environment modeling and decision-making algorithms. Their combination of multiple cores and a built-in radar signal processing sub-system makes them an attractive choice for tasks like front radar processing, sensor fusion hubs, and ''autonomous driving domain controllers'' that must meet ASIL-D safety levels.<ref name="ref14281090102">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
*'''Industrial Automation and Robotics:''' Infineon has also positioned the AURIX family for use in industrial applications that demand high reliability. The TC3xx MCUs, with their hardware self-test mechanisms and safety documentation, can be found in ''industrial motor drives, robotics controllers, and PLCs (programmable logic controllers)'', where they help achieve functional safety certifications up to SIL-3 (according to IEC 61508). The powerful TriCore cores and rich peripheral set enable complex motor control algorithms (e.g., field-oriented control for servo motors) and real-time sensor processing in factory automation. Additionally, the support for automotive-grade networking (CAN/CAN-FD, Ethernet) and timing peripherals makes them suitable for synchronous control in robotics and machinery. Infineon’s provision of AUTOSAR-compatible software for AURIX has even facilitated its use in non-automotive settings such as medical devices and elevator controllers, where proven safety and security are required.<ref name="ref496771205">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref>
*'''Aerospace and Defense:''' The high fault-tolerance and deterministic performance of the AURIX TC3xx architecture also attract interest for aerospace and other mission-critical uses. In avionics systems or autonomous drones, for instance, the lockstep core configuration and robust error checking of AURIX can provide an added layer of reliability for flight control computers or navigation systems. While primarily an automotive chip, its ability to operate in harsh conditions (−40°C to 150°C range) and to detect internal failures in real-time makes it viable for certain aerospace electronic systems. Some defense and aerospace projects leverage COTS (commercial off-the-shelf) automotive components like AURIX for applications such as unmanned vehicle control and high-reliability communication links, given its safety pedigree. (In these domains, additional analysis and possibly radiation testing would be performed if the devices are used in high-altitude or space environments.)
== Architecture Overview ==
[[File:Infineon TC3xx Architecture.webp|545x545px|thumb|alt=TC3xx Architecture Overview|TC3xx Architecture Overview]]
=== Processor Cores and Architecture===
The AURIX TC3xx family implements Infineon’s TriCore™ architecture, which uniquely combines aspects of RISC microcontrollers, DSP (digital signal processor) capabilities, and conventional microprocessor features into a single core design. Each TC3xx device can include up to six independent TriCore 32-bit CPU cores (TriCore version 1.6.2), all capable of running at up to 300 MHz clock frequency. Four of these cores can operate in dual-core lockstep pairs (with one core acting as a redundant checker for its partner) to provide fault detection for safety-critical functions. The TriCore cores use a superscalar Harvard architecture with 32-bit instruction words (and support for mixed 16/32-bit instruction encoding for code density). Each core includes a dedicated Floating Point Unit (FPU) for single-precision arithmetic and supports DSP-oriented instructions (e.g. single-cycle 16×16 MAC operations, SIMD for 16-bit/8-bit data) to accelerate signal processing tasks. For fast real-time performance, the architecture offers low interrupt latency (with automatic context save on-chip) and features like zero-overhead loops and a programmable peripheral timer unit for scheduling tasks. In total, a high-end TC3xx (such as the TC39x) provides six 300 MHz cores plus four checker cores, yielding a theoretical processing throughput of up to ~2400 DMIPS (Dhrystone MIPS) when all cores are utilized. This represents roughly a threefold increase in computational power over the previous AURIX generation (which achieved ~740 DMIPS with three cores).<ref name="ref19484776952">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref><ref name="ref2022357806">UDE Debug, Trace and Test solutions for Infineon TriCore™ AURIX™ TC32, TC33, TC35, TC36, TC37, TC38, TC39, TC3x Microcontrollers https://www.pls-mc.com/products/infineon-tricore-aurix-tc32-tc33-tc35-tc36-tc37-tc38-tc39-microcontrollers/</ref><ref name="ref14281090103">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref>
===Memory Subsystem and Cache===
AURIX TC3xx microcontrollers integrate a large on-chip memory system to meet real-time and safety requirements. Program flash memory sizes range up to 16 MB on the largest models, with over 6 MB of on-chip SRAM available for data and scratchpad usage. Each TriCore CPU has its own tightly-coupled local memories as well as caches: for example, each core includes a 32 KB instruction cache and a 16 KB data cache. In addition, every core has separate local RAM blocks (Harvard architecture) for instructions and data (often termed PSPR and DSPR – Program Scratch-Pad RAM and Data Scratch-Pad RAM) that allow deterministic access for time-critical routines. Shared global memory is provided via a Local Memory Unit (LMU) which can be up to several hundred kilobytes (for instance, 768 KB in the TC39x) accessible by all cores. The memory system is connected by a high-bandwidth internal bus fabric (the SRI crossbar and peripheral buses) that arbitrates access between cores, DMA engines, and peripherals. This architecture ensures that each core can quickly fetch instructions and data either from its local cache/RAM or the central memory, enabling efficient parallel processing. Memory protection hardware is also built-in to isolate tasks of different criticality, an important feature for safety and security.<ref name="ref19484776952" /><ref name="ref5727814512">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>
===Peripherals and Interfaces===
One of the strengths of the AURIX TC3xx architecture is its extensive set of on-chip peripherals and interface controllers, designed to handle the complex networking and I/O needs of modern vehicles and industrial systems. Key peripheral features and interfaces include:<ref name="ref19484776952" /><ref name="ref2022357806" /><ref name="ref14281090103" /><ref name="ref3635926">AURIX Training System Architecture https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_System_Architecture-Training-v01_00-EN.pdf?fileId=5546d46272e49d2a0172eb476d56739e</ref>

* '''Networking Interfaces:''' Multiple CAN FD controllers (supporting up to 12 CAN-FD channels in high-end variants) for in-vehicle networking, with legacy CAN and LIN interfaces (up to 24 LIN channels) for lower-speed device communication. Many TC3xx devices also integrate up to two FlexRay controllers for time-triggered automotive networks (maintaining compatibility with earlier automotive communication standards). For high-bandwidth data, a Gigabit Ethernet MAC is included, enabling uses like automotive Ethernet (e.g., audio-video bridging and IP-based connectivity).
* '''Analog and Timers:''' A suite of analog peripherals including multiple ADC units for sensor interfacing and motor control, and DACs in some models. Sophisticated timer units are on-chip, notably the Generic Timer Module (GTM) and Capture/Compare Units (CCU6), which can generate complex PWM waveforms and handle events for engine control, power inverters, or robotics with minimal CPU intervention. These timers enable precise control of actuators (e.g. fuel injection timing, electric motor commutation) in real time.
*'''Serial Interfaces:''' SPI, I²C, UART/LIN and other serial interfaces for connecting to external sensors, actuator controllers, and memory. The controllers often support multiple instances (several SPI channels, etc.) to accommodate numerous devices. AURIX TC3xx also provides an external bus interface (EBU) for parallel memory or FPGA connectivity, and an SD/MMC interface (eMMC) to connect external flash memory for data logging or over-the-air update storage.
*'''Dedicated Processing Units:''' Some AURIX TC3xx models include special accelerators, such as a hardware Fast Fourier Transform unit (HW-FFT) and up to two Signal Processing Units (SPUs) optimized for radar signal processing. These enable the microcontroller to handle radar front-end data or other intensive DSP tasks (like Fourier transforms for radar or audio signals) on-chip, which is crucial for advanced driver assistance sensors. There is also a ''Security Module'' (covered in a later section) and a Safety Management Unit that supervise system integrity.
*'''Other On-chip Modules:''' Watchdog timers, error-correction coders for memories (ECC on flash and RAM for reliability), a programmable interrupt system, multiple DMA channels (up to 128 DMA channels) for efficient data movement, and debug interfaces (JTAG and a 2/3-pin DAP) for development. The on-chip debug system supports tracing of program execution (via a built-in Emulation Memory, MCDS) to aid in complex multicore software development.

Overall, the AURIX TC3xx provides a highly integrated SoC-like platform, allowing a single chip to manage tasks ranging from powertrain control and chassis control to infotainment gateways. This high level of integration reduces the need for separate companion chips and helps to lower system complexity and cost.
===Performance and Benchmarking===
Fabricated in a 40 nm embedded flash process<ref name="ref2022357806" />, AURIX TC3xx processors achieve significant performance gains over prior generations while maintaining automotive-grade power efficiency. With six 32-bit cores at 300 MHz (four of them paired in lockstep), a flagship TC3xx device (e.g., TC39x) can deliver up to approximately 2,400 DMIPS of aggregate computing throughput<ref name="ref2022357806" />. In terms of per-core performance, the TriCore architecture yields around 1.3–2.0 DMIPS/MHz depending on the instruction mix, meaning each 300 MHz core can approach ~400–600 DMIPS in optimized scenarios<ref name="ref14281090103" /><ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. This is on par with or exceeding many contemporary 32-bit automotive MCUs. The integrated DSP extensions and optional accelerators (like the FFT unit) also enable high-speed signal processing, with Infineon citing up to ~1.8 GFLOPS of DSP throughput for certain operations<ref name="ref1222155140" />.

Real-world performance improvements of the TC3xx over its predecessor are notable: for example, compared to the first-generation AURIX (which offered up to 740 DMIPS), the TC3xx’s expanded core count and clock speed provide roughly three times the computational power on the same type of workload<ref name="ref14281090103" />. This extra headroom allows more functions (such as running multiple control algorithms or sensor fusion tasks in parallel) to be consolidated onto one microcontroller without compromising real-time deadlines<ref name="ref14281090103" />. Despite the increase in speed and core count, the TC3xx family was designed with power and thermal constraints in mind, achieving these gains within similar power consumption envelopes as the previous generation by leveraging the smaller 40 nm process and power-saving features like clock gating<ref name="ref5727814512" />. The deterministic real-time performance (with features like lockstep and tightly-coupled memory) makes the AURIX TC3xx suitable for the most demanding automotive applications, where consistent low latency and high throughput are required simultaneously.

== On-Chip System Connectivity and Bridges ==
[[File:TC3xx On-Chip System Connectivity.png|thumb|The TC3xx has two '''SRI Domains''' (SRI0 and SRI1). CPU0 to CPU3 are connected to SRI0, CPU4/5 are connected to SRI1.|alt=TC3xx On-Chip System Connectivity|423x423px]]
The AURIX™ TC3xx Platform has three independent on-chip connectivity resources:

* '''System Resource Interconnect Fabric (SRI Fabric)''' connects the TriCore CPUs, the DMA module, and other high bandwidth requestors to high bandwidth memories and other resources for instruction fetches and data accesses. A key component of the fabric is the SRI crossbar, which connects all the agents in one SRI domain. The SRI crossbar carries the transactions between the SRI Masters and SRI Slaves of the domain. The SRI crossbar supports parallel transactions between different SRI Master and SRI Slave agents. In addition to the parallelism of concurrent requests, it also supports pipelined requests from an SRI Master to a SRI Slave.
* '''System Peripheral Bus (SPB)''' connects the TriCore CPUs, the DMA module, and other SPB masters to the medium and low bandwidth peripherals. SPB masters do not directly connect to the SRI Fabric, and will access SRI attached resources via a SFI_F2S Bridge.
* '''Back Bone Bus (BBB)''' connects the TriCore CPUs, the DMA module, and SPB masters with ADAS resources. SRI Masters do not directly connect to the BBB, but access BBB attached resources via a SFI_S2F Bridge. SPB masters also do not directly connect to the BBB, but access BBB attached resources via bridging over the SRI Fabric.

=== CPU Resource Access Times ===
These tables describe the CPU access times to various resources in CPU clock cycles for the AURIX™ TC3xx Platform. In the case of load or fetch accesses, the access times are the minimum number of CPU stall cycles to complete the access. If there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

For write access, the access times are the maximum for a sequence of such access (non-conflicting). In many cases for a singleton access, or a short sequence, write buffering reduces the stall effect seen by a CPU, sometimes to 0. However, as with loads and fetches, if there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

==== Access latency for global resources ====
{| class="wikitable"
|+
! CPU Access Type !! CPU stall cycles
!Notes
|-
| Data read from System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
| rowspan="2" |The final number of stall cycles will depend on the real number of WS generated by the target resource.
|-
| Data write to System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC39x, TC37xED) || <math>9 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
| rowspan="2" |When SFI_S2F is connected to XBar2 (TC39x and TC37xED) there is an additional latency due to access going through an S2S.
|-
| Data write to Back Bone Bus (BBB) (TC39x, TC37xED) || <math>5 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC35x, TC33xED) || <math>6 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
|
|-
| Data write to Back Bone Bus (BBB) (TC35x, TC33xED) || <math>3 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|
|}


* '''Module Wait State''': The number of wait states for read and for write accesses is >= 1 and depends on the accessed module and its configuration.


==== CPU Accesses: Stall cycles for local and SRI resources ====
{| class="wikitable"
|+
! CPU Access Type !! Local CPU !! Local SRI !! Remote SRI Domain
|-
| Data read from DSPR || 0 || 7 || 10
|-
| Data write to DSPR || 0 || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from DSPR || See local SRI column || 7 || 10
|-
| Data read from DLMU || 0 || 7 || 10
|-
| Data write to DLMU || 2 || 5, {{rev|3|with Pipelining}}|| 5, 4
|-
| Instruction fetch from DLMU || See local SRI column || 7 || 10
|-
| Data read from PSPR || See local SRI column || 7 || 10
|-
| Data write to PSPR || See local SRI column || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from PSPR || 0 || 7 || 10
|-
| Data read from PFlash || 5 + PWS || 10 + PWS || 13 + PWS
|-
| Instruction fetch from PFlash (buffer miss) || 2 + PWS || 9 + PWS || 12 + PWS
|-
| Instruction fetch from PFlash (buffer hit) || 3 || 6 || 9
|-
| Data read from LMU || n.a. || 7 || 10
|-
| Data write to LMU || n.a. || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from LMU || n.a. || 7 || 10
|-
| Data read from DFlash || n.a. || 5 + 3*(3 + DCWS) || 8 + 3*(3 + DCWS)
|-
| Data read access from EMEM (TC39x, TC37xED) || n.a. || n.a. || 14, {{rev|15|fBBB < fSRI}}
|-
| Data write access to EMEM (TC39x, TC37xED) || n.a. || n.a. || 9
|-
| Data read access from EMEM (TC35x, TC33xED) || n.a. || 11, {{rev|12|fBBB < fSRI}}|| n.a.
|-
| Data write access to EMEM (TC35x, TC33xED) || n.a. || 9 || n.a.
|-
| Data read access from DAM || n.a. || 10 || 13
|-
| Data write access to DAM || n.a. || 7 || 7
|}

* '''Remote SRI Domain''': Only applies to products with SRI extenders. Additional latency due to access going through an S2S
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''DCWS''': Configured DFlash Corrected Wait States (Includes cycles for DFlash access cycles and ECC correction latency)

== CPU Subsystem ==
[[File:TC3xx Processor Core, Local Memory and Connectivity.png|alt=TC3xx Processor Core, Local Memory and Connectivity|thumb|Processor Core, Local Memory and Connectivity]]The Infineon AURIX TC3xx features up to 6 processor cores (CPU0 ... CPU5) implementing the [[TriCore Instruction Set Architecture|TC1.6.2 instruction set architecture]]. The following section focuses on the microarchitectural details of the CPU subsystem. For more information about the ISA, please take a look at the [[TriCore Instruction Set Architecture]].

The processor core connects to the following memories and bus interfaces (where implemented):
*Program Scratch-Pad SRAM (PSPR)
*Data Scratch-Pad SRAM (DSPR)
*Program Cache (PCache)
*Data Cache (DCache)
*Local Memory Unit (DLMU)
*Local Pflash bank (LPB)
*SRI slave interface (x2)
*SRI master Interface
*SPB master interface

=== TC1.6.2P Implementation Features ===
*Most instructions executed in 1 cycle
*Branch instructions in 1, 2 or 3 cycles (using dynamic branch prediction)
*Wide memory interface for fast context switch
* Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
*Six memory protection register sets
*Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
*Third pipeline for loop instruction only (zero overhead loop)
*Single precision Floating Point Unit (IEEE-754 Compatible)
*Dedicated Integer divide unit
*18 data memory protection ranges, 10 code memory protection ranges arranged in 6 sets

=== Superscalar Architecture ===
The processor core within the AURIX TC3xx family, specifically the TC1.6.2P implementation, employs a superscalar architecture characterized by three parallel pipelines: the Integer Pipeline, the Load/Store Pipeline, and the Loop Pipeline. Superscalar execution is a form of instruction-level parallelism that enables the processor to issue and execute multiple instructions during a single clock cycle. The TriCore TC3xx core's superscalar architecture allows it to issue and execute multiple instructions in parallel. Specifically, it can issue up to two instructions simultaneously to the Integer and Load/Store pipelines. However, there are certain constraints on this dual issuing capability. For example, back-to-back data arithmetic instructions can only be issued in separate cycles, and a load/store instruction can be issued either on its own or paired with a data arithmetic instruction, provided the load/store instruction is the second in the pair. Under ideal conditions, with careful instruction scheduling, this dual-issue capability can lead to a throughput of close to 0.5 clock cycles per instruction, effectively executing two instructions per cycle.

=== Pipeline Stages ===
The execution of instructions within the TriCore TC3xx core is managed through a pipeline consisting of several stages. In one document it is mentioned that the pipeline consists of 6 stages <ref name="ref3635926" />, but the exact stages remain unclear. From the architecture the following stages can be inferred:

* '''Fetch Stage''': The initial stage in the pipeline is the Fetch stage, where instructions are retrieved from memory. This task is handled by the Instruction Fetch Unit (IFU), which is responsible for fetching instructions from the memory system. To improve efficiency, the IFU employs a pre-fetching mechanism, anticipating the instructions that will be needed and bringing them into the processor before they are actually required. Instructions are fetched through a 64-bit wide Program Memory Interface (PMI), allowing for the retrieval of a significant amount of instruction data in each cycle. The fetched instructions are then placed into an issue FIFO, a buffer capable of holding up to six instructions. This buffer plays a crucial role in managing the flow of instructions to the subsequent execution pipelines. The 64-bit fetch width and the instruction buffer are indicative of a design that aims to ensure a continuous supply of instructions to the pipelines, preventing them from being starved of work. A wider fetch path allows for more instruction bits to be obtained from memory in each clock cycle, while the buffer helps to mitigate temporary delays in instruction fetching.
* '''Execution Unit''': The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop Pipeline. All three pipelines operate in parallel and are capable of executing instructions simultaneously. Each pipline has its own decode stage and two execute stages. Furthermore, the TC3xx features a Floating Point Unit (FPU). It is not clear whether the FPU is part of the execution unit or a separate unit. It is assumed that the FPU also has its own decode stage and an unknown number of execute stages
** '''Decode Stage''': Following the Fetch stage, the instruction are issued to one of the pipelines. In the decode stage of each pipeline, the instruction is examined and translated to determine the specific operation it represents and to identify the operands it will operate on. It is assumed that operands are read from the register file during the decode stage.
** '''Execute Stage''': The Execute stage is where the actual operation specified by the instruction is carried out. Pipeline hazards (stalls) are minimised by the use of forwarding paths between pipeline stages allowing the results of one instruction to be used by a following instruction as soon as the result becomes available.
** '''Writeback Stage''': The final stage in the pipeline is the Writeback stage. In this stage, the results produced by the executed instruction are written back to the processor's register file, making them available for subsequent instructions. It is unclear whether the writeback stage is part of the (two) execution stages or a separate stage.

=== Execution Pipelines ===
The TriCore TC3xx core leverages four parallel pipelines to enhance its performance. Each pipeline is designed to handle a specific class of instructions:

* '''Integer Pipeline:''' This pipeline is responsible for executing integer arithmetic and logical instructions, including data-conditional jump instructions, bit manipulation operations, as well as division and multiply-accumulate (MAC) instructions.
* '''Load/Store Pipeline:''' The primary function of this pipeline is to manage memory access operations, including loading data from memory and storing data to memory. It also handles address arithmetic, unconditional jump instructions, procedure call instructions, context-switching operations, and control flow related to context save areas (CSAs).
* '''Loop Pipeline:''' This is a specialized pipeline designed to facilitate zero-overhead loops, a technique that significantly improves the performance of iterative code sections. Its design aims to eliminate or minimize the overhead typically associated with loop control, such as incrementing counters and checking loop conditions. Some documentation suggests that the loop pipeline comes along with a "Loop Cache". This dedicated cache would likely be used to store instructions belonging to the loop, enabling very fast access and execution for repeated iterations.
* '''Floating Point Unit (FPU):''' The FPU is responsible for executing floating-point arithmetic operations

=== Store Buffers ===
The TriCore TC3xx core include '''Store Buffers''' to decouple memory write operations from CPU instruction execution. All stores from the Load/Store Pipeline are placed in the store buffer prior to being written to local memory or transferred via the bus system. Write data is taken from the store buffers and written to memory when the target memory or bus interface becomes available. In normal operation the CPU will prioritise memory load operations over store operations in order to improve performance unless the store buffer is full or the order of load and store operations must be preserved (e.g. peripheral space access). The store buffer can hold the data for up to 6 stores operations. To improve performance the store buffer will merge consecutive byte, half-word, and word writes of the same location to reduce the number of memory accesses required.

=== Instruction Timing ===

==Functional Safety and Security Features==
===Hardware Security Module and Encryption===
One of the defining features of the AURIX TC3xx family is its robust hardware-based security subsystem, implemented to protect against cyber threats and unauthorized manipulation of vehicle systems. Each TC3xx MCU includes a dedicated ''Hardware Security Module'' (HSM), which is essentially an on-chip co-processor with its own CPU and cryptographic engine designed to handle secure operations. In the second-generation AURIX (TC3xx), the HSM was upgraded with support for asymmetric cryptography (e.g., RSA, ECC algorithms) in hardware, providing significantly faster public-key encryption and authentication capabilities than pure software implementations. This HSM supports '''EVITA Full''' (the highest level of the EU’s EVITA automotive security requirements), meaning it can perform secure boot, message authentication, and encryption at a level suitable for protecting critical in-vehicle communications. For example, the HSM can encrypt and authenticate CAN/Ethernet messages to prevent spoofing or tampering on the vehicle network, and it can manage cryptographic keys securely isolated from the main application cores.<ref name="ref14281090104">AURIX™ microcontroller TC3xx family of Infineon fuels automated driving and electromobility - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2016/INFATV201610-005.html</ref><ref name="ref2022357806" />

The security module enables features like '''secure boot''', where the AURIX will only execute firmware that is digitally signed by the vehicle manufacturer, thereby preventing unauthorized or malicious code. It also facilitates ''over-the-air (OTA) updates'' in a secure manner: the TC3xx HSM can verify and decrypt update packages received via telematics, allowing firmware upgrades while protecting against attackers attempting to hijack the software. In addition, the HSM includes a true random number generator and supports protocols for immobilizer and theft protection systems. Infineon’s implementation essentially treats the HSM as an “embedded smart card” inside the microcontroller. This approach, building on Infineon’s expertise in chip card security, helps to safeguard sensitive assets like cryptographic keys and to perform secure operations (encryption, decryption, authentication) in hardware, making attacks significantly more difficult. The strong cybersecurity provisions of the AURIX TC3xx have made it a preferred choice for vehicle gateway ECUs and central body controllers, which are points of entry for connected car communications and thus high-value targets for hackers. By incorporating the HSM, automotive OEMs can implement advanced security features such as encrypted onboard communication (to thwart bus tampering) and secure diagnostics, ensuring the vehicle’s electronic data is protected against cyber threats even as cars become more connected.<ref name="ref14281090104" /><ref name="ref5727814513">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref><ref name="ref19484776953">32-bit TriCore™ AURIX™– TC3xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/</ref>
=== Functional Safety and Fault Tolerance===
Beyond cybersecurity, the AURIX TC3xx architecture is built with extensive ''functional safety'' features to meet the highest safety integrity levels in automotive systems. The multi-core design supports ''lockstep operation'', where redundant checker cores run in parallel with main cores and continuously compare results cycle-by-cycle. In TC3xx devices, up to four of the six TriCore CPUs have such lockstep partner cores, allowing the microcontroller to detect any single-point CPU failure instantly (if a discrepancy arises between the core and its checker, a fault is signaled). A ''Safety Management Unit (SMU)'' is integrated on-chip to monitor various fault conditions throughout the device – it aggregates error signals from the lockstep cores, memory ECC monitors, clock/watchdog monitors, and peripheral self-tests, and can initiate safe-state actions (like resetting the chip or signaling an error pin to an external supervisor) if a critical fault is detected. The AURIX safety concept also includes a distributed Memory Protection Unit (MPU) arrangement, with multiple memory protection contexts that prevent errant or malicious code from writing to wrong memory areas. This helps contain faults and eases the integration of software with mixed criticality (Infineon allows partitioning software components of different ASIL levels on the same MCU while keeping them isolated).<ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref19519075552">Safety Microcontrollers: Texas Instruments Hercules vs Infineon AURIX https://www.linkedin.com/pulse/safety-microcontrollers-texas-instruments-hercules-vs-cook-meng-miet</ref>

Crucially, the TC3xx family was developed according to ISO 26262 processes and can achieve '''ASIL-D''' (Automotive Safety Integrity Level D), the highest grade for automotive functional safety. Compared to a traditional dual-core lockstep approach, the AURIX’s multi-core safety architecture allowed Infineon to reduce certain safety development overheads (earlier Infineon data suggested up to 30% reduction in safety software workload) by providing built-in safety mechanisms and diagnostics. Infineon supplies a comprehensive safety manual and diagnostic libraries for the AURIX, helping engineers utilize features like CPU self-tests, RAM tests, and CRC checks to comply with safety standards. In addition to automotive standards, the AURIX TC3xx has also been qualified for '''industrial safety''': in 2023, Infineon announced support for IEC 61508 metrics, enabling designs with AURIX to reach SIL-2 and SIL-3 safety integrity levels for industrial applications. This cross-industry safety compliance is facilitated by the MCU’s redundant design and detailed failure mode documentation (FMEDA) provided by Infineon. In summary, the AURIX TC3xx integrates both proactive safety (fault prevention via lockstep, monitoring and protection) and reactive safety (fault detection and safe shutdown), making it a dependable component for systems that cannot afford unintended behavior, whether in cars, factories, or aerospace. <ref name="ref14281090104" /><ref name="ref5727814513" /><ref name="ref4967712052">Infineon's AURIX™ & TRAVEO™ microcontroller families extend their support for IEC 61508 hardware and software metrics enabling industrial safety up to SIL-3 - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2023/INFATV202303-078.html</ref><ref name="ref196858272">MCUs support industrial functional safety - Electronic Products https://www.electronicproducts.com/mcus-support-industrial-functional-safety/</ref>
== Platform Devices ==
The following table shows a feature overview of the AURIX™ TC3xx Platform family focusing on memory and number of cores.
{| class="wikitable"
!
!Feature
!TC33x
!TC33xEXT
!TC35x
!TC36x
!TC37x
!TC37xEXT
!TC38x
!TC39x
|-
| rowspan="2" |CPUs
|Cores / Checker Cores
|1 / 1
|2 / 1
|3 / 2
|2 / 2
|3 / 2
|3 / 3
|4 / 2
|6 / 4
|-
|Max. Freq.
| colspan="8" |300 MHz
|-
| rowspan="2" |Cache per CPU
|Program [KB]
| colspan="8" |32
|-
|Data [KB]
| colspan="8" |16
|-
| rowspan="3" |SRAM per CPU
|PSPR [KB]
|8
|{{rev|32|CPU0}}
{{rev|64|other}}
|64
|32
|64
|64
|64
|64
|-
|DSPR [KB]
|192
|{{rev|192|CPU0}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|192
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|-
|DLMU [KB]
|8
|{{rev|8|CPU0}}
{{rev|64|other}}
|64
|64
|64
|64
|64
|64
|-
| rowspan="2" |SRAM global
|LMU [KB]
| -
| -
|512
| -
| -
| -
|128
|768
|-
|DAM [KB]
| -
| -
|32
| -
|64
|64
|128
|128
|-
| rowspan="3" |Extension Memory (EMEM)
|TCM [MB]
| -
|1
|2
| -
| -
|2
| -
|2
|-
|XCM [MB]
| -
| -
| -
| -
| -
|1
| -
|2
|-
|XTM [KB]
| -
|16
|16
| -
| -
|16
| -
|16
|-
| rowspan="2" |Program Flash
|Size [MB]
|2
|4
|4
|4
|6
|10
|10
|16
|-
|Banks [MB]
|1 x 2
|2 x 2
|2 x 2
|2 x 2
|2 x 3
|3 x 3, 1 x 1
|3 x 3, 1 x 1
|5 x 3, 1 x 1
|-
| rowspan="2" |Data Flash
|DF0 Size (single-ended) [KB]
|128
|128
|128
|128
|256
|512
|512
|1024
|-
|DF1 Size (single-ended) [KB]
|128
|128
|128
|128
|128
|128
|128
|128
|-
| rowspan="3" |DMA
|Channels
|64
|64
|64
|64
|128
|128
|128
|128
|-
|Move Engines
|2
|2
|2
|2
|2
|2
|2
|2
|-
|Resource Partitions
|4
|4
|4
|4
|4
|4
|4
|4
|}

== Compilers ==
The AURIX TC3xx family is a series of high-performance microcontrollers widely used in automotive and industrial applications. Compilers for the AURIX TC3xx are crucial for developers aiming to optimize performance, reliability, and safety in their applications. One significant aspect of the compiler landscape for AURIX TC3xx is the limited direct support from mainline open-source compilers such as GCC or LLVM/Clang. The primary reason for this is the stringent requirements for functional safety in automotive and industrial applications, which demand specialized features and compliance with safety standards that are often not met by general-purpose open-source compilers.

=== Commercial Compilers ===

# '''Tasking''': Tasking compilers are renowned for their robust support for automotive applications, offering advanced debugging capabilities and optimization techniques tailored for the AURIX architecture. They provide extensive code optimization, comprehensive debugging tools, and strong support for safety standards such as ISO 26262, making them ideal for developing high-performance, reliable, and safe applications.
# '''HighTec''': The HighTec compiler is a popular choice, known for its Eclipse-based development environment and strong multicore support. HighTec provides both GCC and LLVM-based ports of open-source compilers tailored specifically for the AURIX TC3xx family. These compilers offer efficient parallel execution, advanced code analysis, and an integrated development environment, ensuring robust performance and compliance with safety standards.
# '''Green Hills Software''': Green Hills Software provides a highly optimized toolchain aimed at safety-critical applications, focusing on high performance and strict compliance with automotive standards. Their compiler offers superior optimization, extensive safety features, and a proprietary IDE with specialized tools for automotive development, ensuring developers can meet the stringent demands of functional safety.

=== GCC for AURIX ===

While mainline GCC does not directly support the AURIX TC3xx family, there is an unofficial GCC version available for AURIX. Due to the GNU General Public License (GPL), the source code from HighTec was retrieved and, along with binary versions, published on GitHub:

*GCC 4.9.4/Binutils 2.20/Newlib 1.18 for Tricore Aurix [[https://github.com/volumit/package_494 Source]] [[https://github.com/volumit/tricore_gcc494_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc494_linux_bins Prebuild Linux Binaries]]
*GCC 9.4.0/Binutils 2.20/Newlib 1.18 for Tricore Aurix [[https://github.com/volumit/package_940 Source]] [[https://github.com/volumit/tricore_gcc940_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc940_linux_bins Prebuild Linux Binaries]]
*GDB 10.0.50 for Tricore Aurix [[https://github.com/volumit/gdb-tricore Source]]
==emmtrix Tools for AURIX TC3xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX TC3xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

==See Also==

*[[Infineon AURIX TC4x]]
*[[Infineon AURIX TC2xx]]
*[[TriCore Instruction Set Architecture]]

==External Links==

*https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/
*[https://documentation.infineon.com/aurixtc3xx/docs/qmd1702366622648 AURIX TC3xx user manuals]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d3605221d96 AURIX™ TC3xx User Manual Part-1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d35f8541d94 AURIX™ TC3xx User Manual Part-2]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd AURIX™ TC3xx Architecture vol 1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 AURIX™ TC3xx Architecture vol 2]

== References ==
<references />
[[Category:Supported Architectures]]

{{#seo:
|title=Infineon AURIX TC3xx Family – Deep Dive
|description=This deep dive into Infineon's AURIX TC3xx family explores its multi-core TriCore architecture, real-time capabilities, safety and security features and tools
|image=File:AURIX_TC399_LFBGA-516_plain.jpg
|keywords=AURIX, Infineon, TC3xx, microcontroller, TriCore, automotive, ADAS, ISO 26262, functional safety, embedded security, ASIL-D, deep dive
}}

Infineon AURIX TC2xx

2025-03-28T11:43:25Z

Mira.steinmetz:

'''Infineon AURIX TC2xx''' is a family of 32-bit automotive microcontrollers developed by Infineon Technologies. ''AURIX'' stands for ''“Automotive Realtime Integrated Next Generation Architecture”'', reflecting its design for real-time, safety-critical automotive applications<ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. The TC2xx series (first-generation AURIX) is based on a multicore architecture featuring up to three independent 32-bit '''TriCore''' processor cores. Introduced around 2012, the AURIX TC2xx marked Infineon’s transition to a multicore microcontroller platform (fabricated in 65 nm technology) after earlier single-core TriCore generations. It was designed from the ground up to meet stringent automotive safety requirements (ISO 26262) and to provide higher performance and integration for applications like engine management, chassis control, and driver assistance systems.<ref name="ref1222155140" /><ref name="ref1490396573">Optimized for Success - EE Times Europe https://www.eetimes.eu/optimized-for-success/</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>

The AURIX TC2xx family’s design philosophy is to combine '''safety''', '''security''', and '''performance''' in one scalable MCU platform. It achieves high functional safety compliance (up to '''ASIL-D''', the highest automotive safety integrity level) with less development effort compared to traditional dual-controller lockstep systems<ref name="ref572781451" />. Infineon claims that using AURIX can cut safety-related development time by ~30% versus classical lockstep architectures, thanks to its built-in fault detection and monitoring hardware. At the same time, the TC2xx provides significant performance headroom – roughly 50% to 100% higher computational performance compared to its predecessors – while maintaining power consumption similar to previous single-core designs. To address emerging automotive security needs, the AURIX MCUs also integrate a dedicated Hardware Security Module ('''HSM''') on-chip, which protects against IP theft, fraud, and tampering. This combination of features makes the AURIX TC2xx a popular choice for consolidating various automotive control functions (powertrain, safety, body, etc.) onto one platform, without sacrificing reliability or efficiency.<ref name="ref572781451" /><ref name="ref71179009">32-bit TriCore™ AURIX™– TC2xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/</ref>
==Architecture==
The AURIX TC2xx is built on Infineon’s '''TriCore''' architecture, which uniquely unifies traits of a RISC processor, a microcontroller, and a DSP (digital signal processor) into one core design. Each TriCore CPU in the TC2xx is a 32-bit superscalar processor that supports both 32-bit and 16-bit instruction formats (the latter for code size efficiency). The TriCore instruction set architecture includes typical RISC features (load/store architecture, 4 GB address space) and DSP capabilities (such as multiply-accumulate instructions and bit manipulation) in a single core. The cores also have an optional floating-point unit (FPU) and support SIMD (single-instruction multiple-data) operations for signal processing acceleration. The maximum core frequency in the TC2xx family is 300 MHz, and devices achieve about 1.7–2.4 DMIPS/MHz per core, providing robust real-time performance.<ref name="ref1222155140" /><ref name="ref71179009" />

In terms of core configuration, high-end AURIX TC2xx models implement three main TriCore CPUs, which can be run in parallel or in redundant (lockstep) pairs for safety. Some variants include a redundant checker core that shadows a primary core to detect calculation errors (a technique to meet SIL/ASIL safety goals). The multicore architecture is supported by a layered memory system: each TriCore has tightly coupled local memory for fast instruction and data access, and they share access to large on-chip Flash and RAM via an internal bus matrix. Memory options in the TC2xx range from about '''0.5 MB up to 8 MB of on-chip Flash''', and from ~50 KB up to 2.7 MB of SRAM, depending on the specific device. This on-chip memory (with ECC protection on memories for safety) allows real-time code execution and data storage without external memory in most use cases. For peripherals and I/O, the AURIX architecture includes a rich set of on-chip modules connected via internal buses, such as analog-to-digital converters, timer units, communication interfaces, and direct memory access (DMA) controllers. AURIX TC2xx MCUs typically provide interfaces like multiple CAN/CAN-FD channels, LIN/UART, SPI, I²C, Ethernet (on higher-end models), and automotive-specific buses (e.g. FlexRay on some variants), making the chip a self-contained controller for complex automotive networks.'''<ref name="ref572781451" />'''<ref name="ref71179009" /><ref name="ref957370148">Infineon TriCore - Wikipedia https://en.wikipedia.org/wiki/Infineon_TriCore</ref>

The '''Generic Timer Module (GTM)''' is a notable part of the AURIX TC2xx architecture. It is a sophisticated timer/co-processor integrated on-chip to handle complex timing, PWM generation, input capture, and other signal conditioning tasks across more than 200 channels. There are also specialized accelerators and co-processors on certain TC2xx devices, such as a '''Hardware Fast Fourier Transform (HFFT)''' unit for signal processing and a '''Parallel Pixel Processor''' for simple video or sensor data processing. These dedicated engines offload the TriCore CPUs for specific high-load tasks (e.g. radar signal FFTs or encoder signal processing), improving overall throughput in automotive applications. The AURIX architecture uses a single-power supply (5V or 3.3V) design and includes an on-chip voltage regulator (EVR), simplifying power management. The MCUs are offered in a variety of package types (from compact QFP-64 up to large BGA-516) to accommodate different I/O needs. Overall, the TC2xx architecture is highly integrated and optimized for real-time, combining multiple CPU cores with ample flash memory, SRAM, and peripherals on one chip to serve as a '''central control unit''' in vehicles.<ref name="ref1222155140" /><ref>Aurix Unleashed - RS Components https://docs.rs-online.com/0f3f/0900766b815c315c.pdf</ref>
==Key Features==

* '''Safety Mechanisms:''' The AURIX TC2xx was developed via an ISO 26262-compliant process and includes multiple hardware mechanisms to achieve '''functional safety up to ASIL-D'''. Notably, it supports ''lockstep'' operation, where one or two of the TriCore CPUs can run in redundant lockstep mode with another core to detect discrepancies (faults) cycle-by-cycle. A Safety Management Unit ('''SMU''') is built in to monitor critical system parameters and handle faults. The architecture employs memory protection units and safe internal communication buses to isolate and supervise different software domains. Other safety features include '''error-correcting code (ECC)''' on flash and RAM, redundant peripherals (for example, duplicated ADC channels), watchdog timers, clock and voltage monitors, and self-test routines. These features allow developers to more easily implement safety-critical functions and meet standards like IEC 61508 (SIL-3) or ISO 26262 (ASIL-D) using a single AURIX MCU, whereas achieving the same on a traditional single-core MCU might require additional external safety ICs or companion processors.<ref name="ref1490396573" /><ref name="ref572781451" />
* '''Security Functions:''' Infineon integrated a dedicated Hardware Security Module ('''HSM''') into the AURIX TC2xx family to address automotive cybersecurity requirements. This HSM is essentially an on-chip co-processor (with its own CPU and flash) that handles cryptographic operations and secure key storage isolated from the main cores. It follows the EVITA (E-safety Vehicle Intrusion Protected Applications) guidelines for automotive security. The HSM enables features like secure boot, encryption/decryption, authentication, and detection of software tampering. By having a built-in “embedded smart card” for security, the AURIX can implement anti-theft, anti-cloning, and secure onboard communication measures without needing an external security chip. This integration is a key differentiator, as it helps protect vehicle functions (e.g. immobilizers, firmware updates, V2X communication) against hacking and unauthorized modifications.<ref name="ref1222155140" /><ref name="ref71179009" />
* '''Performance and DSP Capability:''' Each TriCore CPU in the TC2xx is capable of up to 300 MHz operation, and combined the multicore setup offers considerable processing power for an MCU (Infineon cites up to ~1.8 GFLOPS of DSP throughput for the highest models). The TriCore design delivers around '''1.7–2.4 DMIPS/MHz''' per core, meaning a triple-core AURIX at max frequency can exceed 2000 DMIPS of total throughput. The inclusion of DSP instructions and dedicated accelerators enables the AURIX to handle computationally intensive tasks (like control algorithms, filtering operations, or even rudimentary neural networks) that previously might require a separate DSP or FPGA. A built-in '''Floating Point Unit''' on each core supports single-precision (and optional double-precision in some cases) arithmetic, beneficial for model-based control algorithms and automotive sensor processing. Peripherals like the '''Generic Timer Module (GTM)''' and '''Hardware FFT''' accelerator (available on select TC2xx variants) further boost real-time performance for handling high-frequency events (e.g. engine ignition timing, motor control PWM, radar signal analysis) without overloading the CPU. Despite the performance, the TC2xx was designed with efficiency in mind; Infineon managed to double the performance over the prior generation (TC1xx AUDO) while keeping power consumption at comparable levels. The MCUs also support various low-power modes and a standby controller to minimize energy usage when parts of the system are idle.<ref name="ref1222155140" /><ref name="ref572781451" />
* '''Power and Integration:''' As a system-on-chip for vehicles, AURIX TC2xx integrates a wide range of '''communication interfaces''' and analog/digital peripherals. Common features include multiple CAN bus controllers (often with CAN FD support), LIN/UART, SPI and I²C channels, FlexRay communication in high-end models, and even Ethernet (in variants aimed at gateway or ADAS roles). High-resolution '''ADC units''' (with shared and redundant channels) allow precise sensor measurements for engine or chassis control. There are also specialized modules like delta-sigma ADCs and SENT interfaces for automotive sensor inputs. This rich peripheral set reduces the need for external components, helping to lower the overall system Bill of Materials. The TC2xx devices operate over a broad temperature range (typically –40 °C to +150 °C), meeting the demands of under-the-hood automotive environments. They run from a single supply (with internal regulators), simplifying designs, and support both 5 V and 3.3 V systems for compatibility with a variety of sensors and actuators. Combined with its safety and security features, the AURIX’s high integration makes it a one-chip solution for many complex embedded applications.<ref name="ref1222155140" /><ref name="ref1490396573" /><ref name="ref71179009" /><ref name="ref957370148" />

==Applications==
The Infineon AURIX TC2xx family is primarily targeted at the '''automotive industry''', especially domains requiring high reliability and real-time control. Its initial use cases were in '''powertrain''' and engine management systems – for example, controlling combustion engines, managing fuel injection and ignition, and coordinating electric motor and battery systems in hybrid or electric vehicles. The multi-core AURIX can run multiple control algorithms in parallel (e.g. for an engine’s cylinders, transmission and motor inverter concurrently), which is valuable in modern electrified powertrains. Beyond engines, AURIX TC2xx MCUs are used in '''chassis and safety systems''': they can serve as the central controller for '''anti-lock braking systems (ABS)''' and stability control, '''airbag control units''', '''electric power steering (EPS)''' systems, and suspension controllers. Advanced Driver Assistance Systems ('''ADAS''') and autonomous driving modules in earlier generations of vehicles have also employed AURIX for tasks such as sensor fusion, radar signal processing, and acting as a safety supervisor for driving assistance features<ref name="ref572781451" />. For example, a radar unit for adaptive cruise control might use an AURIX to perform real-time signal processing (using its DSP capabilities and HFFT) and make high-level decisions, all within an ASIL-D safe environment.<ref name="ref572781451" /><ref name="ref1228701036">https://resources.tasking.com/sites/default/files/2021-02/Take%20Advantage%20of%20Infineon%20AURIX%20TC3xx%20Family%20With%20the%20Right%20Compiler_WEB.pdf</ref>

Thanks to its safety certification and robust design, the AURIX TC2xx has seen adoption in any application that cannot tolerate failure. This includes '''industrial automation and robotics''', where the MCU’s reliability and support for functional safety (IEC 61508) are attractive. In industrial motor drives or robotics controllers, an AURIX might handle precise motor control algorithms and system monitoring. Other use cases outside pure automotive include '''commercial vehicles and transportation''' (trucks, agricultural and construction machinery), which have similar safety and durability requirements. The AURIX’s extensive communication interfaces also make it suitable as a gateway or central node in complex networks – for instance, acting as a domain controller in modern automotive E/E architectures to coordinate data between powertrain, body, and ADAS subsystems. Some '''electric vehicle (EV)''' platforms use AURIX MCUs in battery management systems and inverter controls, leveraging its calculation power for battery algorithms and its safety for monitoring cell health. In summary, the TC2xx family finds use in scenarios that demand '''real-time performance with high safety integrity''', predominantly in automotive (engine, transmission, chassis, safety, ADAS) but also in high-end industrial embedded systems.<ref name="ref71179009" /><ref name="ref1228701036" />

==emmtrix Tools for AURIX TC2xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX TC2xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ TC2xx / [[Infineon AURIX TC3xx|TC3xx]]/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

== See Also ==

* [[Infineon AURIX TC3xx]]
* [[Infineon AURIX TC4x]]
* [[TriCore Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/
* [https://www.infineon.com/dgdl/Infineon-TC29x_B-step-UM-v01_03-EN.pdf?fileId=5546d46269bda8df0169ca1bdee424a2 TC29x B-Step User Manual]

== References ==
<references />
[[Category:Supported Architectures]]

Infineon AURIX TC4x

2025-03-28T11:42:47Z

Mira.steinmetz:

[[File:Infineon Aurix TC4x.webp|right|frameless]]
The TC4x is Infineon's latest generation of AURIX™ microcontrollers, designed for advanced automotive applications, including eMobility, Advanced Driver Assistance Systems (ADAS), and automotive E/E (Electric/Electronic) architectures. These microcontrollers are built on a 28 nm process and feature the [[TriCore Instruction Set Architecture|TriCore™ 1.8 instruction set architecture]], which includes up to six cores running at speeds up to 500 MHz. This architecture is optimized for high-performance and real-time applications.

== Key Features ==
* '''High Performance and Scalability''': Equipped with a Parallel Processing Unit (PPU), Data Routing Engine (DRE), and other accelerators to enhance AI capabilities and real-time processing.
* '''Extensive Connectivity''': Supports high-speed communication interfaces such as 5 Gbps Ethernet, PCIe, CAN-XL, and 10BASE-T1S Ethernet, providing flexibility and performance for various automotive applications.
* '''Enhanced Security''': Compliant with ISO 21434, the TC4x includes advanced cybersecurity modules and supports safe, over-the-air (SOTA) updates with zero downtime.
* '''Memory and Storage''': Features up to 25 MB of on-chip flash memory, allowing for complex software applications and data storage.
* '''Real-Time Control''': Advanced timers and ADCs (Analog-to-Digital Converters) improve control loops for electric motors and power conversion tasks.

== Architecture ==
[[File:Infineon TC4x Architecture.png|thumb|Infineon TC4x architecture|494x494px]]

=== System Architecture ===

=== TC 1.8P Processor Core (CPU0 ... CPU5) ===

=== Parallel Processing Unit (PPU) ===
The PPU is an implementation of the '''DesignWare ARC EV71 Processor'''. The length of the vector registers is flexible and depends on the version. Commercially, 128 or 256 bit vector registers are available. In a pre-series stepping even 512 bit was used.

== Applications ==
* eMobility
* ADAS
* Automotive E/E architectures
* Affordable artificial intelligence (AI) applications

== emmtrix Tools for AURIX TC4x ==
emmtrix offers several tools for the Infineon AURIX TC4x architecture:

* [https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer] for vectorizing C code for the Infineon PPU. emmtrix was working together with Infineon already during develop of the TC4x architecture for supporting the PPU and received one of the first series A test boards.
* [https://www.emmtrix.com/tools/emmtrix-performance-estimatorator emmtrix Performance Estimator] for estimating the performance of C code written for the Tricore CPUs.

[[File:Infineon Board.png|thumb|Infineon Development Board (AURIX™ TC4x Communication Board)]]

=== emmtrix Code Vectorizer ===
[https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer (eCV)] simplifies programming the Parallel Processing Unit (PPU) on Infineon’s '''AURIX™ TC4x microcontrollers''', enabling significant acceleration of data-parallel applications like sensor fusion or AI inference. By leveraging the PPU, these tasks can be accelerated by factors >10, unlocking the full potential of hardware capabilities.

eCV automates the vectorization process, transforming sequential C code into optimized vectorized code tailored to the '''AURIX™ TC4x architecture'''. This includes efficient handling of memory layouts and advanced loop transformations. Developers can simulate and test functionality even without access to target hardware, reducing development time and effort.

With support for '''Simulink® models, ONNX-based AI workflows,''' and detailed performance insights through integrated simulators, eCV minimizes the need for manual optimization while maximizing hardware performance.[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the '''Infineon AURIX™ microcontroller family''' and has been actively collaborating with Infineon for the past five years.]]

=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / [[Infineon AURIX TC3xx|TC3xx]]/ TC4x microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

== See Also ==

* [[Infineon AURIX TC3xx]]
* [[TriCore Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc4x/

[[Category:Supported Architectures]]

Infineon AURIX TC2xx

2025-03-27T12:58:37Z

Mira.steinmetz: /* emmtrix Tools for AURIX TC3xx */

'''Infineon AURIX TC2xx''' is a family of 32-bit automotive microcontrollers developed by Infineon Technologies. ''AURIX'' stands for ''“Automotive Realtime Integrated Next Generation Architecture”'', reflecting its design for real-time, safety-critical automotive applications<ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. The TC2xx series (first-generation AURIX) is based on a multicore architecture featuring up to three independent 32-bit '''TriCore''' processor cores. Introduced around 2012, the AURIX TC2xx marked Infineon’s transition to a multicore microcontroller platform (fabricated in 65 nm technology) after earlier single-core TriCore generations. It was designed from the ground up to meet stringent automotive safety requirements (ISO 26262) and to provide higher performance and integration for applications like engine management, chassis control, and driver assistance systems.<ref name="ref1222155140" /><ref name="ref1490396573">Optimized for Success - EE Times Europe https://www.eetimes.eu/optimized-for-success/</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>

The AURIX TC2xx family’s design philosophy is to combine '''safety''', '''security''', and '''performance''' in one scalable MCU platform. It achieves high functional safety compliance (up to '''ASIL-D''', the highest automotive safety integrity level) with less development effort compared to traditional dual-controller lockstep systems<ref name="ref572781451" />. Infineon claims that using AURIX can cut safety-related development time by ~30% versus classical lockstep architectures, thanks to its built-in fault detection and monitoring hardware. At the same time, the TC2xx provides significant performance headroom – roughly 50% to 100% higher computational performance compared to its predecessors – while maintaining power consumption similar to previous single-core designs. To address emerging automotive security needs, the AURIX MCUs also integrate a dedicated Hardware Security Module ('''HSM''') on-chip, which protects against IP theft, fraud, and tampering. This combination of features makes the AURIX TC2xx a popular choice for consolidating various automotive control functions (powertrain, safety, body, etc.) onto one platform, without sacrificing reliability or efficiency.<ref name="ref572781451" /><ref name="ref71179009">32-bit TriCore™ AURIX™– TC2xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/</ref>
==Architecture==
The AURIX TC2xx is built on Infineon’s '''TriCore''' architecture, which uniquely unifies traits of a RISC processor, a microcontroller, and a DSP (digital signal processor) into one core design. Each TriCore CPU in the TC2xx is a 32-bit superscalar processor that supports both 32-bit and 16-bit instruction formats (the latter for code size efficiency). The TriCore instruction set architecture includes typical RISC features (load/store architecture, 4 GB address space) and DSP capabilities (such as multiply-accumulate instructions and bit manipulation) in a single core. The cores also have an optional floating-point unit (FPU) and support SIMD (single-instruction multiple-data) operations for signal processing acceleration. The maximum core frequency in the TC2xx family is 300 MHz, and devices achieve about 1.7–2.4 DMIPS/MHz per core, providing robust real-time performance.<ref name="ref1222155140" /><ref name="ref71179009" />

In terms of core configuration, high-end AURIX TC2xx models implement three main TriCore CPUs, which can be run in parallel or in redundant (lockstep) pairs for safety. Some variants include a redundant checker core that shadows a primary core to detect calculation errors (a technique to meet SIL/ASIL safety goals). The multicore architecture is supported by a layered memory system: each TriCore has tightly coupled local memory for fast instruction and data access, and they share access to large on-chip Flash and RAM via an internal bus matrix. Memory options in the TC2xx range from about '''0.5 MB up to 8 MB of on-chip Flash''', and from ~50 KB up to 2.7 MB of SRAM, depending on the specific device. This on-chip memory (with ECC protection on memories for safety) allows real-time code execution and data storage without external memory in most use cases. For peripherals and I/O, the AURIX architecture includes a rich set of on-chip modules connected via internal buses, such as analog-to-digital converters, timer units, communication interfaces, and direct memory access (DMA) controllers. AURIX TC2xx MCUs typically provide interfaces like multiple CAN/CAN-FD channels, LIN/UART, SPI, I²C, Ethernet (on higher-end models), and automotive-specific buses (e.g. FlexRay on some variants), making the chip a self-contained controller for complex automotive networks.'''<ref name="ref572781451" />'''<ref name="ref71179009" /><ref name="ref957370148">Infineon TriCore - Wikipedia https://en.wikipedia.org/wiki/Infineon_TriCore</ref>

The '''Generic Timer Module (GTM)''' is a notable part of the AURIX TC2xx architecture. It is a sophisticated timer/co-processor integrated on-chip to handle complex timing, PWM generation, input capture, and other signal conditioning tasks across more than 200 channels. There are also specialized accelerators and co-processors on certain TC2xx devices, such as a '''Hardware Fast Fourier Transform (HFFT)''' unit for signal processing and a '''Parallel Pixel Processor''' for simple video or sensor data processing. These dedicated engines offload the TriCore CPUs for specific high-load tasks (e.g. radar signal FFTs or encoder signal processing), improving overall throughput in automotive applications. The AURIX architecture uses a single-power supply (5V or 3.3V) design and includes an on-chip voltage regulator (EVR), simplifying power management. The MCUs are offered in a variety of package types (from compact QFP-64 up to large BGA-516) to accommodate different I/O needs. Overall, the TC2xx architecture is highly integrated and optimized for real-time, combining multiple CPU cores with ample flash memory, SRAM, and peripherals on one chip to serve as a '''central control unit''' in vehicles.<ref name="ref1222155140" /><ref>Aurix Unleashed - RS Components https://docs.rs-online.com/0f3f/0900766b815c315c.pdf</ref>
==Key Features==

* '''Safety Mechanisms:''' The AURIX TC2xx was developed via an ISO 26262-compliant process and includes multiple hardware mechanisms to achieve '''functional safety up to ASIL-D'''. Notably, it supports ''lockstep'' operation, where one or two of the TriCore CPUs can run in redundant lockstep mode with another core to detect discrepancies (faults) cycle-by-cycle. A Safety Management Unit ('''SMU''') is built in to monitor critical system parameters and handle faults. The architecture employs memory protection units and safe internal communication buses to isolate and supervise different software domains. Other safety features include '''error-correcting code (ECC)''' on flash and RAM, redundant peripherals (for example, duplicated ADC channels), watchdog timers, clock and voltage monitors, and self-test routines. These features allow developers to more easily implement safety-critical functions and meet standards like IEC 61508 (SIL-3) or ISO 26262 (ASIL-D) using a single AURIX MCU, whereas achieving the same on a traditional single-core MCU might require additional external safety ICs or companion processors.<ref name="ref1490396573" /><ref name="ref572781451" />
* '''Security Functions:''' Infineon integrated a dedicated Hardware Security Module ('''HSM''') into the AURIX TC2xx family to address automotive cybersecurity requirements. This HSM is essentially an on-chip co-processor (with its own CPU and flash) that handles cryptographic operations and secure key storage isolated from the main cores. It follows the EVITA (E-safety Vehicle Intrusion Protected Applications) guidelines for automotive security. The HSM enables features like secure boot, encryption/decryption, authentication, and detection of software tampering. By having a built-in “embedded smart card” for security, the AURIX can implement anti-theft, anti-cloning, and secure onboard communication measures without needing an external security chip. This integration is a key differentiator, as it helps protect vehicle functions (e.g. immobilizers, firmware updates, V2X communication) against hacking and unauthorized modifications.<ref name="ref1222155140" /><ref name="ref71179009" />
* '''Performance and DSP Capability:''' Each TriCore CPU in the TC2xx is capable of up to 300 MHz operation, and combined the multicore setup offers considerable processing power for an MCU (Infineon cites up to ~1.8 GFLOPS of DSP throughput for the highest models). The TriCore design delivers around '''1.7–2.4 DMIPS/MHz''' per core, meaning a triple-core AURIX at max frequency can exceed 2000 DMIPS of total throughput. The inclusion of DSP instructions and dedicated accelerators enables the AURIX to handle computationally intensive tasks (like control algorithms, filtering operations, or even rudimentary neural networks) that previously might require a separate DSP or FPGA. A built-in '''Floating Point Unit''' on each core supports single-precision (and optional double-precision in some cases) arithmetic, beneficial for model-based control algorithms and automotive sensor processing. Peripherals like the '''Generic Timer Module (GTM)''' and '''Hardware FFT''' accelerator (available on select TC2xx variants) further boost real-time performance for handling high-frequency events (e.g. engine ignition timing, motor control PWM, radar signal analysis) without overloading the CPU. Despite the performance, the TC2xx was designed with efficiency in mind; Infineon managed to double the performance over the prior generation (TC1xx AUDO) while keeping power consumption at comparable levels. The MCUs also support various low-power modes and a standby controller to minimize energy usage when parts of the system are idle.<ref name="ref1222155140" /><ref name="ref572781451" />
* '''Power and Integration:''' As a system-on-chip for vehicles, AURIX TC2xx integrates a wide range of '''communication interfaces''' and analog/digital peripherals. Common features include multiple CAN bus controllers (often with CAN FD support), LIN/UART, SPI and I²C channels, FlexRay communication in high-end models, and even Ethernet (in variants aimed at gateway or ADAS roles). High-resolution '''ADC units''' (with shared and redundant channels) allow precise sensor measurements for engine or chassis control. There are also specialized modules like delta-sigma ADCs and SENT interfaces for automotive sensor inputs. This rich peripheral set reduces the need for external components, helping to lower the overall system Bill of Materials. The TC2xx devices operate over a broad temperature range (typically –40 °C to +150 °C), meeting the demands of under-the-hood automotive environments. They run from a single supply (with internal regulators), simplifying designs, and support both 5 V and 3.3 V systems for compatibility with a variety of sensors and actuators. Combined with its safety and security features, the AURIX’s high integration makes it a one-chip solution for many complex embedded applications.<ref name="ref1222155140" /><ref name="ref1490396573" /><ref name="ref71179009" /><ref name="ref957370148" />

==Applications==
The Infineon AURIX TC2xx family is primarily targeted at the '''automotive industry''', especially domains requiring high reliability and real-time control. Its initial use cases were in '''powertrain''' and engine management systems – for example, controlling combustion engines, managing fuel injection and ignition, and coordinating electric motor and battery systems in hybrid or electric vehicles. The multi-core AURIX can run multiple control algorithms in parallel (e.g. for an engine’s cylinders, transmission and motor inverter concurrently), which is valuable in modern electrified powertrains. Beyond engines, AURIX TC2xx MCUs are used in '''chassis and safety systems''': they can serve as the central controller for '''anti-lock braking systems (ABS)''' and stability control, '''airbag control units''', '''electric power steering (EPS)''' systems, and suspension controllers. Advanced Driver Assistance Systems ('''ADAS''') and autonomous driving modules in earlier generations of vehicles have also employed AURIX for tasks such as sensor fusion, radar signal processing, and acting as a safety supervisor for driving assistance features<ref name="ref572781451" />. For example, a radar unit for adaptive cruise control might use an AURIX to perform real-time signal processing (using its DSP capabilities and HFFT) and make high-level decisions, all within an ASIL-D safe environment.<ref name="ref572781451" /><ref name="ref1228701036">https://resources.tasking.com/sites/default/files/2021-02/Take%20Advantage%20of%20Infineon%20AURIX%20TC3xx%20Family%20With%20the%20Right%20Compiler_WEB.pdf</ref>

Thanks to its safety certification and robust design, the AURIX TC2xx has seen adoption in any application that cannot tolerate failure. This includes '''industrial automation and robotics''', where the MCU’s reliability and support for functional safety (IEC 61508) are attractive. In industrial motor drives or robotics controllers, an AURIX might handle precise motor control algorithms and system monitoring. Other use cases outside pure automotive include '''commercial vehicles and transportation''' (trucks, agricultural and construction machinery), which have similar safety and durability requirements. The AURIX’s extensive communication interfaces also make it suitable as a gateway or central node in complex networks – for instance, acting as a domain controller in modern automotive E/E architectures to coordinate data between powertrain, body, and ADAS subsystems. Some '''electric vehicle (EV)''' platforms use AURIX MCUs in battery management systems and inverter controls, leveraging its calculation power for battery algorithms and its safety for monitoring cell health. In summary, the TC2xx family finds use in scenarios that demand '''real-time performance with high safety integrity''', predominantly in automotive (engine, transmission, chassis, safety, ADAS) but also in high-end industrial embedded systems.<ref name="ref71179009" /><ref name="ref1228701036" />

==emmtrix Tools for AURIX TC2xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is Infineon Associated Partner, has over 10 years of experience working with Infineon and their '''AURIX™ microcontroller family''' and has been collaborating for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX TC2xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ TC2xx / [[Infineon AURIX TC3xx|TC3xx]]/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

== See Also ==

* [[Infineon AURIX TC3xx]]
* [[Infineon AURIX TC4x]]
* [[TriCore Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/
* [https://www.infineon.com/dgdl/Infineon-TC29x_B-step-UM-v01_03-EN.pdf?fileId=5546d46269bda8df0169ca1bdee424a2 TC29x B-Step User Manual]

== References ==
<references />
[[Category:Supported Architectures]]

Infineon AURIX TC2xx

2025-03-27T12:55:53Z

Mira.steinmetz: /* Applications */

'''Infineon AURIX TC2xx''' is a family of 32-bit automotive microcontrollers developed by Infineon Technologies. ''AURIX'' stands for ''“Automotive Realtime Integrated Next Generation Architecture”'', reflecting its design for real-time, safety-critical automotive applications<ref name="ref1222155140">Infineon AURIX - Wikipedia https://en.wikipedia.org/wiki/Infineon_AURIX</ref>. The TC2xx series (first-generation AURIX) is based on a multicore architecture featuring up to three independent 32-bit '''TriCore''' processor cores. Introduced around 2012, the AURIX TC2xx marked Infineon’s transition to a multicore microcontroller platform (fabricated in 65 nm technology) after earlier single-core TriCore generations. It was designed from the ground up to meet stringent automotive safety requirements (ISO 26262) and to provide higher performance and integration for applications like engine management, chassis control, and driver assistance systems.<ref name="ref1222155140" /><ref name="ref1490396573">Optimized for Success - EE Times Europe https://www.eetimes.eu/optimized-for-success/</ref><ref name="ref572781451">Safety Joins Performance: Infineon Introduces Automotive Multicore 32-bit Microcontroller Family AURIX™ to Meet Safety and Powertrain Requirements of Upcoming Vehicle Generations - Infineon Technologies https://www.infineon.com/cms/en/about-infineon/press/market-news/2012/INFATV201205-040.html</ref>

The AURIX TC2xx family’s design philosophy is to combine '''safety''', '''security''', and '''performance''' in one scalable MCU platform. It achieves high functional safety compliance (up to '''ASIL-D''', the highest automotive safety integrity level) with less development effort compared to traditional dual-controller lockstep systems<ref name="ref572781451" />. Infineon claims that using AURIX can cut safety-related development time by ~30% versus classical lockstep architectures, thanks to its built-in fault detection and monitoring hardware. At the same time, the TC2xx provides significant performance headroom – roughly 50% to 100% higher computational performance compared to its predecessors – while maintaining power consumption similar to previous single-core designs. To address emerging automotive security needs, the AURIX MCUs also integrate a dedicated Hardware Security Module ('''HSM''') on-chip, which protects against IP theft, fraud, and tampering. This combination of features makes the AURIX TC2xx a popular choice for consolidating various automotive control functions (powertrain, safety, body, etc.) onto one platform, without sacrificing reliability or efficiency.<ref name="ref572781451" /><ref name="ref71179009">32-bit TriCore™ AURIX™– TC2xx - Infineon Technologies https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/</ref>
==Architecture==
The AURIX TC2xx is built on Infineon’s '''TriCore''' architecture, which uniquely unifies traits of a RISC processor, a microcontroller, and a DSP (digital signal processor) into one core design. Each TriCore CPU in the TC2xx is a 32-bit superscalar processor that supports both 32-bit and 16-bit instruction formats (the latter for code size efficiency). The TriCore instruction set architecture includes typical RISC features (load/store architecture, 4 GB address space) and DSP capabilities (such as multiply-accumulate instructions and bit manipulation) in a single core. The cores also have an optional floating-point unit (FPU) and support SIMD (single-instruction multiple-data) operations for signal processing acceleration. The maximum core frequency in the TC2xx family is 300 MHz, and devices achieve about 1.7–2.4 DMIPS/MHz per core, providing robust real-time performance.<ref name="ref1222155140" /><ref name="ref71179009" />

In terms of core configuration, high-end AURIX TC2xx models implement three main TriCore CPUs, which can be run in parallel or in redundant (lockstep) pairs for safety. Some variants include a redundant checker core that shadows a primary core to detect calculation errors (a technique to meet SIL/ASIL safety goals). The multicore architecture is supported by a layered memory system: each TriCore has tightly coupled local memory for fast instruction and data access, and they share access to large on-chip Flash and RAM via an internal bus matrix. Memory options in the TC2xx range from about '''0.5 MB up to 8 MB of on-chip Flash''', and from ~50 KB up to 2.7 MB of SRAM, depending on the specific device. This on-chip memory (with ECC protection on memories for safety) allows real-time code execution and data storage without external memory in most use cases. For peripherals and I/O, the AURIX architecture includes a rich set of on-chip modules connected via internal buses, such as analog-to-digital converters, timer units, communication interfaces, and direct memory access (DMA) controllers. AURIX TC2xx MCUs typically provide interfaces like multiple CAN/CAN-FD channels, LIN/UART, SPI, I²C, Ethernet (on higher-end models), and automotive-specific buses (e.g. FlexRay on some variants), making the chip a self-contained controller for complex automotive networks.'''<ref name="ref572781451" />'''<ref name="ref71179009" /><ref name="ref957370148">Infineon TriCore - Wikipedia https://en.wikipedia.org/wiki/Infineon_TriCore</ref>

The '''Generic Timer Module (GTM)''' is a notable part of the AURIX TC2xx architecture. It is a sophisticated timer/co-processor integrated on-chip to handle complex timing, PWM generation, input capture, and other signal conditioning tasks across more than 200 channels. There are also specialized accelerators and co-processors on certain TC2xx devices, such as a '''Hardware Fast Fourier Transform (HFFT)''' unit for signal processing and a '''Parallel Pixel Processor''' for simple video or sensor data processing. These dedicated engines offload the TriCore CPUs for specific high-load tasks (e.g. radar signal FFTs or encoder signal processing), improving overall throughput in automotive applications. The AURIX architecture uses a single-power supply (5V or 3.3V) design and includes an on-chip voltage regulator (EVR), simplifying power management. The MCUs are offered in a variety of package types (from compact QFP-64 up to large BGA-516) to accommodate different I/O needs. Overall, the TC2xx architecture is highly integrated and optimized for real-time, combining multiple CPU cores with ample flash memory, SRAM, and peripherals on one chip to serve as a '''central control unit''' in vehicles.<ref name="ref1222155140" /><ref>Aurix Unleashed - RS Components https://docs.rs-online.com/0f3f/0900766b815c315c.pdf</ref>
==Key Features==

* '''Safety Mechanisms:''' The AURIX TC2xx was developed via an ISO 26262-compliant process and includes multiple hardware mechanisms to achieve '''functional safety up to ASIL-D'''. Notably, it supports ''lockstep'' operation, where one or two of the TriCore CPUs can run in redundant lockstep mode with another core to detect discrepancies (faults) cycle-by-cycle. A Safety Management Unit ('''SMU''') is built in to monitor critical system parameters and handle faults. The architecture employs memory protection units and safe internal communication buses to isolate and supervise different software domains. Other safety features include '''error-correcting code (ECC)''' on flash and RAM, redundant peripherals (for example, duplicated ADC channels), watchdog timers, clock and voltage monitors, and self-test routines. These features allow developers to more easily implement safety-critical functions and meet standards like IEC 61508 (SIL-3) or ISO 26262 (ASIL-D) using a single AURIX MCU, whereas achieving the same on a traditional single-core MCU might require additional external safety ICs or companion processors.<ref name="ref1490396573" /><ref name="ref572781451" />
* '''Security Functions:''' Infineon integrated a dedicated Hardware Security Module ('''HSM''') into the AURIX TC2xx family to address automotive cybersecurity requirements. This HSM is essentially an on-chip co-processor (with its own CPU and flash) that handles cryptographic operations and secure key storage isolated from the main cores. It follows the EVITA (E-safety Vehicle Intrusion Protected Applications) guidelines for automotive security. The HSM enables features like secure boot, encryption/decryption, authentication, and detection of software tampering. By having a built-in “embedded smart card” for security, the AURIX can implement anti-theft, anti-cloning, and secure onboard communication measures without needing an external security chip. This integration is a key differentiator, as it helps protect vehicle functions (e.g. immobilizers, firmware updates, V2X communication) against hacking and unauthorized modifications.<ref name="ref1222155140" /><ref name="ref71179009" />
* '''Performance and DSP Capability:''' Each TriCore CPU in the TC2xx is capable of up to 300 MHz operation, and combined the multicore setup offers considerable processing power for an MCU (Infineon cites up to ~1.8 GFLOPS of DSP throughput for the highest models). The TriCore design delivers around '''1.7–2.4 DMIPS/MHz''' per core, meaning a triple-core AURIX at max frequency can exceed 2000 DMIPS of total throughput. The inclusion of DSP instructions and dedicated accelerators enables the AURIX to handle computationally intensive tasks (like control algorithms, filtering operations, or even rudimentary neural networks) that previously might require a separate DSP or FPGA. A built-in '''Floating Point Unit''' on each core supports single-precision (and optional double-precision in some cases) arithmetic, beneficial for model-based control algorithms and automotive sensor processing. Peripherals like the '''Generic Timer Module (GTM)''' and '''Hardware FFT''' accelerator (available on select TC2xx variants) further boost real-time performance for handling high-frequency events (e.g. engine ignition timing, motor control PWM, radar signal analysis) without overloading the CPU. Despite the performance, the TC2xx was designed with efficiency in mind; Infineon managed to double the performance over the prior generation (TC1xx AUDO) while keeping power consumption at comparable levels. The MCUs also support various low-power modes and a standby controller to minimize energy usage when parts of the system are idle.<ref name="ref1222155140" /><ref name="ref572781451" />
* '''Power and Integration:''' As a system-on-chip for vehicles, AURIX TC2xx integrates a wide range of '''communication interfaces''' and analog/digital peripherals. Common features include multiple CAN bus controllers (often with CAN FD support), LIN/UART, SPI and I²C channels, FlexRay communication in high-end models, and even Ethernet (in variants aimed at gateway or ADAS roles). High-resolution '''ADC units''' (with shared and redundant channels) allow precise sensor measurements for engine or chassis control. There are also specialized modules like delta-sigma ADCs and SENT interfaces for automotive sensor inputs. This rich peripheral set reduces the need for external components, helping to lower the overall system Bill of Materials. The TC2xx devices operate over a broad temperature range (typically –40 °C to +150 °C), meeting the demands of under-the-hood automotive environments. They run from a single supply (with internal regulators), simplifying designs, and support both 5 V and 3.3 V systems for compatibility with a variety of sensors and actuators. Combined with its safety and security features, the AURIX’s high integration makes it a one-chip solution for many complex embedded applications.<ref name="ref1222155140" /><ref name="ref1490396573" /><ref name="ref71179009" /><ref name="ref957370148" />

==Applications==
The Infineon AURIX TC2xx family is primarily targeted at the '''automotive industry''', especially domains requiring high reliability and real-time control. Its initial use cases were in '''powertrain''' and engine management systems – for example, controlling combustion engines, managing fuel injection and ignition, and coordinating electric motor and battery systems in hybrid or electric vehicles. The multi-core AURIX can run multiple control algorithms in parallel (e.g. for an engine’s cylinders, transmission and motor inverter concurrently), which is valuable in modern electrified powertrains. Beyond engines, AURIX TC2xx MCUs are used in '''chassis and safety systems''': they can serve as the central controller for '''anti-lock braking systems (ABS)''' and stability control, '''airbag control units''', '''electric power steering (EPS)''' systems, and suspension controllers. Advanced Driver Assistance Systems ('''ADAS''') and autonomous driving modules in earlier generations of vehicles have also employed AURIX for tasks such as sensor fusion, radar signal processing, and acting as a safety supervisor for driving assistance features<ref name="ref572781451" />. For example, a radar unit for adaptive cruise control might use an AURIX to perform real-time signal processing (using its DSP capabilities and HFFT) and make high-level decisions, all within an ASIL-D safe environment.<ref name="ref572781451" /><ref name="ref1228701036">https://resources.tasking.com/sites/default/files/2021-02/Take%20Advantage%20of%20Infineon%20AURIX%20TC3xx%20Family%20With%20the%20Right%20Compiler_WEB.pdf</ref>

Thanks to its safety certification and robust design, the AURIX TC2xx has seen adoption in any application that cannot tolerate failure. This includes '''industrial automation and robotics''', where the MCU’s reliability and support for functional safety (IEC 61508) are attractive. In industrial motor drives or robotics controllers, an AURIX might handle precise motor control algorithms and system monitoring. Other use cases outside pure automotive include '''commercial vehicles and transportation''' (trucks, agricultural and construction machinery), which have similar safety and durability requirements. The AURIX’s extensive communication interfaces also make it suitable as a gateway or central node in complex networks – for instance, acting as a domain controller in modern automotive E/E architectures to coordinate data between powertrain, body, and ADAS subsystems. Some '''electric vehicle (EV)''' platforms use AURIX MCUs in battery management systems and inverter controls, leveraging its calculation power for battery algorithms and its safety for monitoring cell health. In summary, the TC2xx family finds use in scenarios that demand '''real-time performance with high safety integrity''', predominantly in automotive (engine, transmission, chassis, safety, ADAS) but also in high-end industrial embedded systems.<ref name="ref71179009" /><ref name="ref1228701036" />

==emmtrix Tools for AURIX TC3xx==
[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is Infineon Associated Partner, has over 10 years of experience working with Infineon and their '''AURIX™ microcontroller family''' and has been collaborating for the past five years.|alt=emmtrix Associated Partner]]
emmtrix offers the following tool for the Infineon AURIX TC3xx architecture:
=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

== See Also ==

* [[Infineon AURIX TC3xx]]
* [[Infineon AURIX TC4x]]
* [[TriCore Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/
* [https://www.infineon.com/dgdl/Infineon-TC29x_B-step-UM-v01_03-EN.pdf?fileId=5546d46269bda8df0169ca1bdee424a2 TC29x B-Step User Manual]

== References ==
<references />
[[Category:Supported Architectures]]

emmtrix Performance Estimator

2025-03-26T09:02:34Z

Mira.steinmetz: /* Processor Pipeline: */

emmtrix Performance Estimator

2025-03-26T09:01:57Z

Mira.steinmetz:

[https://www.emmtrix.com/tools/emmtrix-performance-estimator emmtrix Performance Estimator (ePE)] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / [https://emmtrix.com/wiki/Infineon_AURIX_TC3xx TC3xx]/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

=== Estimation Methods ===
In general, the execution time of a task or block can be modelled as:

''texec = execution_frequencyblock* single_durationblock''

The C code based static code analysis derives the execution frequency by analyzing loop boundaries using constant folding. For the duration, each instruction in the code is modeled as the number of cycles of an abstract hardware model of the processor, and then summed.

ePE offers three accuracy levels:
*analysis of C code
*generically compiler-optimized code
*assembly code from the target compiler.
Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

==== Static Code Analysis: ====
[[File:Static Code Analysis.jpg|frameless|800x800px]]

==== Processor Pipeline: ====
[[File:ePE Processor Pipeline.png|frameless|950x950px]]
[https://www.emmtrix.com/tools/emmtrix-performance-estimator emmtrix Performance Estimator (ePE)] supports different ways to acquire the duration of the tasks of an application. These methods vary in accuracy and additional software or hardware requirements. Static code analysis provides basic information without the need for hardware or special software and may thus be seamlessly incorporated into early stages of the Software Development Life Cycle (SDLC). More accurate numbers can be collected with interfaces to simulators or the hardware. Depending on the requirements, the methods can be combined as desired.

Addressing performance issues at the onset of the SDLC is not only proactive but also cost-efficient. Early estimation and intervention, as suggested by the below graph, can drastically reduce the complexities and expenses associated with fixing defects post-deployment. Although early estimates may not be as precise as measurements taken during later stages, they serve as a crucial checkpoint to prevent potential timing issues from escalating. This preemptive approach aligns with the principle that the cost to repair defects increases exponentially as they progress through the SDLC, as shown by the sharp rise in cost depicted in the graph. Hence, initial performance estimations are a strategic investment, minimizing the risk of facing a steep climb in remediation costs and efforts at later stages.
[[File:DefectDetectionandRemediation.webp|center|frameless|800x800px|Cost of Defect Remediation across the Software Development Life Cycle]]
[[Category:emmtrix Tools]]

File:Static Code Analysis.jpg

2025-03-26T08:52:06Z

Mira.steinmetz:

File:ePE Processor Pipeline.png

2025-03-26T08:51:24Z

Mira.steinmetz:

Infineon AURIX TC4x

2025-03-24T11:02:11Z

Mira.steinmetz: /* emmtrix Performance Estimator */

[[File:Infineon Aurix TC4x.webp|right|frameless]]
The TC4x is Infineon's latest generation of AURIX™ microcontrollers, designed for advanced automotive applications, including eMobility, Advanced Driver Assistance Systems (ADAS), and automotive E/E (Electric/Electronic) architectures. These microcontrollers are built on a 28 nm process and feature the [[TriCore Instruction Set Architecture|TriCore™ 1.8 instruction set architecture]], which includes up to six cores running at speeds up to 500 MHz. This architecture is optimized for high-performance and real-time applications.

== Key Features ==
* '''High Performance and Scalability''': Equipped with a Parallel Processing Unit (PPU), Data Routing Engine (DRE), and other accelerators to enhance AI capabilities and real-time processing.
* '''Extensive Connectivity''': Supports high-speed communication interfaces such as 5 Gbps Ethernet, PCIe, CAN-XL, and 10BASE-T1S Ethernet, providing flexibility and performance for various automotive applications.
* '''Enhanced Security''': Compliant with ISO 21434, the TC4x includes advanced cybersecurity modules and supports safe, over-the-air (SOTA) updates with zero downtime.
* '''Memory and Storage''': Features up to 25 MB of on-chip flash memory, allowing for complex software applications and data storage.
* '''Real-Time Control''': Advanced timers and ADCs (Analog-to-Digital Converters) improve control loops for electric motors and power conversion tasks.

== Architecture ==
[[File:Infineon TC4x Architecture.png|thumb|Infineon TC4x architecture|494x494px]]

=== System Architecture ===

=== TC 1.8P Processor Core (CPU0 ... CPU5) ===

=== Parallel Processing Unit (PPU) ===
The PPU is an implementation of the '''DesignWare ARC EV71 Processor'''. The length of the vector registers is flexible and depends on the version. Commercially, 128 or 256 bit vector registers are available. In a pre-series stepping even 512 bit was used.

== Applications ==
* eMobility
* ADAS
* Automotive E/E architectures
* Affordable artificial intelligence (AI) applications

== emmtrix Tools for AURIX TC4x ==
emmtrix offers several tools for the Infineon AURIX TC4x architecture:

* [https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer] for vectorizing C code for the Infineon PPU. emmtrix was working together with Infineon already during develop of the TC4x architecture for supporting the PPU and received one of the first series A test boards.
* [https://www.emmtrix.com/tools/emmtrix-performance-estimatorator emmtrix Performance Estimator] for estimating the performance of C code written for the Tricore CPUs.

[[File:Infineon Board.png|thumb|Infineon Development Board (AURIX™ TC4x Communication Board)]]

=== emmtrix Code Vectorizer ===
[https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer (eCV)] simplifies programming the Parallel Processing Unit (PPU) on Infineon’s '''AURIX™ TC4x microcontrollers''', enabling significant acceleration of data-parallel applications like sensor fusion or AI inference. By leveraging the PPU, these tasks can be accelerated by factors >10, unlocking the full potential of hardware capabilities.

eCV automates the vectorization process, transforming sequential C code into optimized vectorized code tailored to the '''AURIX™ TC4x architecture'''. This includes efficient handling of memory layouts and advanced loop transformations. Developers can simulate and test functionality even without access to target hardware, reducing development time and effort.

With support for '''Simulink® models, ONNX-based AI workflows,''' and detailed performance insights through integrated simulators, eCV minimizes the need for manual optimization while maximizing hardware performance.[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is Infineon Associated Partnership, has over 10 years of experience working with Infineon and their '''AURIX™ microcontroller family''' and has been collaborating for the past five years.]]

=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / [[Infineon AURIX TC3xx|TC3xx]]/ TC4x microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

== See Also ==

* [[Infineon AURIX TC3xx]]
* [[TriCore Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc4x/

[[Category:Supported Architectures]]

Infineon AURIX TC4x

2025-03-24T10:27:42Z

Mira.steinmetz: /* emmtrix Code Vectorizer */

[[File:Infineon Aurix TC4x.webp|right|frameless]]
The TC4x is Infineon's latest generation of AURIX™ microcontrollers, designed for advanced automotive applications, including eMobility, Advanced Driver Assistance Systems (ADAS), and automotive E/E (Electric/Electronic) architectures. These microcontrollers are built on a 28 nm process and feature the [[TriCore Instruction Set Architecture|TriCore™ 1.8 instruction set architecture]], which includes up to six cores running at speeds up to 500 MHz. This architecture is optimized for high-performance and real-time applications.

== Key Features ==
* '''High Performance and Scalability''': Equipped with a Parallel Processing Unit (PPU), Data Routing Engine (DRE), and other accelerators to enhance AI capabilities and real-time processing.
* '''Extensive Connectivity''': Supports high-speed communication interfaces such as 5 Gbps Ethernet, PCIe, CAN-XL, and 10BASE-T1S Ethernet, providing flexibility and performance for various automotive applications.
* '''Enhanced Security''': Compliant with ISO 21434, the TC4x includes advanced cybersecurity modules and supports safe, over-the-air (SOTA) updates with zero downtime.
* '''Memory and Storage''': Features up to 25 MB of on-chip flash memory, allowing for complex software applications and data storage.
* '''Real-Time Control''': Advanced timers and ADCs (Analog-to-Digital Converters) improve control loops for electric motors and power conversion tasks.

== Architecture ==
[[File:Infineon TC4x Architecture.png|thumb|Infineon TC4x architecture|494x494px]]

=== System Architecture ===

=== TC 1.8P Processor Core (CPU0 ... CPU5) ===

=== Parallel Processing Unit (PPU) ===
The PPU is an implementation of the '''DesignWare ARC EV71 Processor'''. The length of the vector registers is flexible and depends on the version. Commercially, 128 or 256 bit vector registers are available. In a pre-series stepping even 512 bit was used.

== Applications ==
* eMobility
* ADAS
* Automotive E/E architectures
* Affordable artificial intelligence (AI) applications

== emmtrix Tools for AURIX TC4x ==
emmtrix offers several tools for the Infineon AURIX TC4x architecture:

* [https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer] for vectorizing C code for the Infineon PPU. emmtrix was working together with Infineon already during develop of the TC4x architecture for supporting the PPU and received one of the first series A test boards.
* [https://www.emmtrix.com/tools/emmtrix-performance-estimatorator emmtrix Performance Estimator] for estimating the performance of C code written for the Tricore CPUs.

[[File:Infineon Board.png|thumb|Infineon Development Board (AURIX™ TC4x Communication Board)]]

=== emmtrix Code Vectorizer ===
[https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer (eCV)] simplifies programming the Parallel Processing Unit (PPU) on Infineon’s '''AURIX™ TC4x microcontrollers''', enabling significant acceleration of data-parallel applications like sensor fusion or AI inference. By leveraging the PPU, these tasks can be accelerated by factors >10, unlocking the full potential of hardware capabilities.

eCV automates the vectorization process, transforming sequential C code into optimized vectorized code tailored to the '''AURIX™ TC4x architecture'''. This includes efficient handling of memory layouts and advanced loop transformations. Developers can simulate and test functionality even without access to target hardware, reducing development time and effort.

With support for '''Simulink® models, ONNX-based AI workflows,''' and detailed performance insights through integrated simulators, eCV minimizes the need for manual optimization while maximizing hardware performance.[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is Infineon Associated Partnership, has over 10 years of experience working with Infineon and their '''AURIX™ microcontroller family''' and has been collaborating for the past five years.]]

=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

== See Also ==

* [[Infineon AURIX TC3xx]]
* [[TriCore Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc4x/

[[Category:Supported Architectures]]

File:Infineon Board.png

2025-03-24T10:23:55Z

Mira.steinmetz:

Infineon AURIX TC4x

2025-03-24T10:11:42Z

Mira.steinmetz: /* emmtrix Tools for AURIX TC4x */

[[File:Infineon Aurix TC4x.webp|right|frameless]]
The TC4x is Infineon's latest generation of AURIX™ microcontrollers, designed for advanced automotive applications, including eMobility, Advanced Driver Assistance Systems (ADAS), and automotive E/E (Electric/Electronic) architectures. These microcontrollers are built on a 28 nm process and feature the [[TriCore Instruction Set Architecture|TriCore™ 1.8 instruction set architecture]], which includes up to six cores running at speeds up to 500 MHz. This architecture is optimized for high-performance and real-time applications.

== Key Features ==
* '''High Performance and Scalability''': Equipped with a Parallel Processing Unit (PPU), Data Routing Engine (DRE), and other accelerators to enhance AI capabilities and real-time processing.
* '''Extensive Connectivity''': Supports high-speed communication interfaces such as 5 Gbps Ethernet, PCIe, CAN-XL, and 10BASE-T1S Ethernet, providing flexibility and performance for various automotive applications.
* '''Enhanced Security''': Compliant with ISO 21434, the TC4x includes advanced cybersecurity modules and supports safe, over-the-air (SOTA) updates with zero downtime.
* '''Memory and Storage''': Features up to 25 MB of on-chip flash memory, allowing for complex software applications and data storage.
* '''Real-Time Control''': Advanced timers and ADCs (Analog-to-Digital Converters) improve control loops for electric motors and power conversion tasks.

== Architecture ==
[[File:Infineon TC4x Architecture.png|thumb|Infineon TC4x architecture|494x494px]]

=== System Architecture ===

=== TC 1.8P Processor Core (CPU0 ... CPU5) ===

=== Parallel Processing Unit (PPU) ===
The PPU is an implementation of the '''DesignWare ARC EV71 Processor'''. The length of the vector registers is flexible and depends on the version. Commercially, 128 or 256 bit vector registers are available. In a pre-series stepping even 512 bit was used.

== Applications ==
* eMobility
* ADAS
* Automotive E/E architectures
* Affordable artificial intelligence (AI) applications

== emmtrix Tools for AURIX TC4x ==
emmtrix offers several tools for the Infineon AURIX TC4x architecture:

* [https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer] for vectorizing C code for the Infineon PPU. emmtrix was working together with Infineon already during develop of the TC4x architecture for supporting the PPU and received one of the first series A test boards.
* [https://www.emmtrix.com/tools/emmtrix-performance-estimatorator emmtrix Performance Estimator] for estimating the performance of C code written for the Tricore CPUs.

=== emmtrix Code Vectorizer ===
[https://www.emmtrix.com/tools/emmtrix-code-vectorizer emmtrix Code Vectorizer (eCV)] simplifies programming the Parallel Processing Unit (PPU) on Infineon’s '''AURIX™ TC4x microcontrollers''', enabling significant acceleration of data-parallel applications like sensor fusion or AI inference. By leveraging the PPU, these tasks can be accelerated by factors >10, unlocking the full potential of hardware capabilities.

eCV automates the vectorization process, transforming sequential C code into optimized vectorized code tailored to the '''AURIX™ TC4x architecture'''. This includes efficient handling of memory layouts and advanced loop transformations. Developers can simulate and test functionality even without access to target hardware, reducing development time and effort.

With support for '''Simulink® models, ONNX-based AI workflows,''' and detailed performance insights through integrated simulators, eCV minimizes the need for manual optimization while maximizing hardware performance.[[File:lowres-Signet Associated Partner EN.eps.png|thumb|305x305px|emmtrix Technologies is Infineon Associated Partnership, has over 10 years of experience working with Infineon and their '''AURIX™ microcontroller family''' and has been collaborating for the past five years.]]

=== emmtrix Performance Estimator ===
[[emmtrix Performance Estimator|emmtrix Performance Estimator (ePE)]] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ [[Infineon AURIX TC2xx|TC2xx]] / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

=== Services ===

== See Also ==

* [[Infineon AURIX TC3xx]]
* [[TriCore Instruction Set Architecture]]

== External Links ==

* https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc4x/

[[Category:Supported Architectures]]

Infineon AURIX TC4x

2025-03-24T10:06:27Z

Mira.steinmetz: /* emmtrix Tools for AURIX TC4x */

Infineon AURIX TC3xx

2025-03-20T12:54:10Z

Mira.steinmetz:

== Architecture ==
[[File:Infineon TC3xx Architecture.webp|center|frameless|844x844px]]

=== On-Chip System Connectivity and Bridges ===
[[File:TC3xx On-Chip System Connectivity.png|thumb|SRI Domains]]
The AURIX™ TC3xx Platform has three independent on-chip connectivity resources:

* '''System Resource Interconnect Fabric (SRI Fabric)''' connects the TriCore CPUs, the DMA module, and other high bandwidth requestors to high bandwidth memories and other resources for instruction fetches and data accesses. A key component of the fabric is the SRI crossbar, which connects all the agents in one SRI domain. The SRI crossbar carries the transactions between the SRI Masters and SRI Slaves of the domain. The SRI crossbar supports parallel transactions between different SRI Master and SRI Slave agents. In addition to the parallelism of concurrent requests, it also supports pipelined requests from an SRI Master to a SRI Slave.
* '''System Peripheral Bus (SPB)''' connects the TriCore CPUs, the DMA module, and other SPB masters to the medium and low bandwidth peripherals. SPB masters do not directly connect to the SRI Fabric, and will access SRI attached resources via a SFI_F2S Bridge.
* '''Back Bone Bus (BBB)''' connects the TriCore CPUs, the DMA module, and SPB masters with ADAS resources. SRI Masters do not directly connect to the BBB, but access BBB attached resources via a SFI_S2F Bridge. SPB masters also do not directly connect to the BBB, but access BBB attached resources via bridging over the SRI Fabric.

=== CPU Resource Access Times ===
These tables describe the CPU access times to various resources in CPU clock cycles for the AURIX™ TC3xx Platform. In the case of load or fetch accesses, the access times are the minimum number of CPU stall cycles to complete the access. If there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

For write access, the access times are the maximum for a sequence of such access (non-conflicting). In many cases for a singleton access, or a short sequence, write buffering reduces the stall effect seen by a CPU, sometimes to 0. However, as with loads and fetches, if there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

==== Access latency for global resources ====
{| class="wikitable"
|+
! CPU Access Type !! CPU stall cycles
!Notes
|-
| Data read from System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
| rowspan="2" |The final number of stall cycles will depend on the real number of WS generated by the target resource.
|-
| Data write to System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC39x, TC37xED) || <math>9 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
| rowspan="2" |When SFI_S2F is connected to XBar2 (TC39x and TC37xED) there is an additional latency due to access going through an S2S.
|-
| Data write to Back Bone Bus (BBB) (TC39x, TC37xED) || <math>5 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC35x, TC33xED) || <math>6 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
|
|-
| Data write to Back Bone Bus (BBB) (TC35x, TC33xED) || <math>3 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|
|}


* '''Module Wait State''': The number of wait states for read and for write accesses is >= 1 and depends on the accessed module and its configuration.


==== CPU Accesses: Stall cycles for local and SRI resources ====
{| class="wikitable"
|+
! CPU Access Type !! Local CPU !! Local SRI !! Remote SRI Domain
|-
| Data read from DSPR || 0 || 7 || 10
|-
| Data write to DSPR || 0 || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from DSPR || See local SRI column || 7 || 10
|-
| Data read from DLMU || 0 || 7 || 10
|-
| Data write to DLMU || 2 || 5, {{rev|3|with Pipelining}}|| 5, 4
|-
| Instruction fetch from DLMU || See local SRI column || 7 || 10
|-
| Data read from PSPR || See local SRI column || 7 || 10
|-
| Data write to PSPR || See local SRI column || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from PSPR || 0 || 7 || 10
|-
| Data read from PFlash || 5 + PWS || 10 + PWS || 13 + PWS
|-
| Instruction fetch from PFlash (buffer miss) || 2 + PWS || 9 + PWS || 12 + PWS
|-
| Instruction fetch from PFlash (buffer hit) || 3 || 6 || 9
|-
| Data read from LMU || n.a. || 7 || 10
|-
| Data write to LMU || n.a. || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from LMU || n.a. || 7 || 10
|-
| Data read from DFlash || n.a. || 5 + 3*(3 + DCWS) || 8 + 3*(3 + DCWS)
|-
| Data read access from EMEM (TC39x, TC37xED) || n.a. || n.a. || 14, {{rev|15|fBBB < fSRI}}
|-
| Data write access to EMEM (TC39x, TC37xED) || n.a. || n.a. || 9
|-
| Data read access from EMEM (TC35x, TC33xED) || n.a. || 11, {{rev|12|fBBB < fSRI}}|| n.a.
|-
| Data write access to EMEM (TC35x, TC33xED) || n.a. || 9 || n.a.
|-
| Data read access from DAM || n.a. || 10 || 13
|-
| Data write access to DAM || n.a. || 7 || 7
|}

* '''Remote SRI Domain''': Only applies to products with SRI extenders. Additional latency due to access going through an S2S
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''DCWS''': Configured DFlash Corrected Wait States (Includes cycles for DFlash access cycles and ECC correction latency)

== CPU Subsystem (CPU0 ... CPU5) ==
[[File:TC3xx Processor Core, Local Memory and Connectivity.png|alt=TC3xx Processor Core, Local Memory and Connectivity|thumb|Processor Core, Local Memory and Connectivity]]The Infineon AURIX TC3xx features up to 6 processor cores implementing the [[Tricore TC1.6.2 Instruction Set Architecture|TC1.6.2 instruction set architecture]]. The following section focuses on the microarchitectural details of the CPU subsystem. For more information about the ISA, please take a look at the [[Tricore Instruction Set Architecture|TC1.6.2 article]].

The processor core connects to the following memories and bus interfaces (where implemented):
*Program Scratch-Pad SRAM (PSPR)
*Data Scratch-Pad SRAM (DSPR)
*Program Cache (PCache)
*Data Cache (DCache)
*Local Memory Unit (DLMU)
*Local Pflash bank (LPB)
*SRI slave interface (x2)
*SRI master Interface
*SPB master interface

=== TC1.6.2P Implementation Features ===
*Most instructions executed in 1 cycle
*Branch instructions in 1, 2 or 3 cycles (using dynamic branch prediction)
*Wide memory interface for fast context switch
* Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
*Six memory protection register sets
*Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
*Third pipeline for loop instruction only (zero overhead loop)
*Single precision Floating Point Unit (IEEE-754 Compatible)
*Dedicated Integer divide unit
*18 data memory protection ranges, 10 code memory protection ranges arranged in 6 sets

=== Pipeline ===

=== Instruction Timing ===

== Platform Devices ==
The following table shows a feature overview of the AURIX™ TC3xx Platform family focusing on memory and number of cores.
{| class="wikitable"
!
!Feature
!TC33x
!TC33xEXT
!TC35x
!TC36x
!TC37x
!TC37xEXT
!TC38x
!TC39x
|-
| rowspan="2" |CPUs
|Cores / Checker Cores
|1 / 1
|2 / 1
|3 / 2
|2 / 2
|3 / 2
|3 / 3
|4 / 2
|6 / 4
|-
|Max. Freq.
| colspan="8" |300 MHz
|-
| rowspan="2" |Cache per CPU
|Program [KB]
| colspan="8" |32
|-
|Data [KB]
| colspan="8" |16
|-
| rowspan="3" |SRAM per CPU
|PSPR [KB]
|8
|{{rev|32|CPU0}}
{{rev|64|other}}
|64
|32
|64
|64
|64
|64
|-
|DSPR [KB]
|192
|{{rev|192|CPU0}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|192
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|-
|DLMU [KB]
|8
|{{rev|8|CPU0}}
{{rev|64|other}}
|64
|64
|64
|64
|64
|64
|-
| rowspan="2" |SRAM global
|LMU [KB]
| -
| -
|512
| -
| -
| -
|128
|768
|-
|DAM [KB]
| -
| -
|32
| -
|64
|64
|128
|128
|-
| rowspan="3" |Extension Memory (EMEM)
|TCM [MB]
| -
|1
|2
| -
| -
|2
| -
|2
|-
|XCM [MB]
| -
| -
| -
| -
| -
|1
| -
|2
|-
|XTM [KB]
| -
|16
|16
| -
| -
|16
| -
|16
|-
| rowspan="2" |Program Flash
|Size [MB]
|2
|4
|4
|4
|6
|10
|10
|16
|-
|Banks [MB]
|1 x 2
|2 x 2
|2 x 2
|2 x 2
|2 x 3
|3 x 3, 1 x 1
|3 x 3, 1 x 1
|5 x 3, 1 x 1
|-
| rowspan="2" |Data Flash
|DF0 Size (single-ended) [KB]
|128
|128
|128
|128
|256
|512
|512
|1024
|-
|DF1 Size (single-ended) [KB]
|128
|128
|128
|128
|128
|128
|128
|128
|-
| rowspan="3" |DMA
|Channels
|64
|64
|64
|64
|128
|128
|128
|128
|-
|Move Engines
|2
|2
|2
|2
|2
|2
|2
|2
|-
|Resource Partitions
|4
|4
|4
|4
|4
|4
|4
|4
|}

== Compilers ==
The AURIX TC3xx family is a series of high-performance microcontrollers widely used in automotive and industrial applications. Compilers for the AURIX TC3xx are crucial for developers aiming to optimize performance, reliability, and safety in their applications. One significant aspect of the compiler landscape for AURIX TC3xx is the limited direct support from mainline open-source compilers such as GCC or LLVM/Clang. The primary reason for this is the stringent requirements for functional safety in automotive and industrial applications, which demand specialized features and compliance with safety standards that are often not met by general-purpose open-source compilers.

=== Commercial Compilers ===

# '''Tasking''': Tasking compilers are renowned for their robust support for automotive applications, offering advanced debugging capabilities and optimization techniques tailored for the AURIX architecture. They provide extensive code optimization, comprehensive debugging tools, and strong support for safety standards such as ISO 26262, making them ideal for developing high-performance, reliable, and safe applications.
# '''HighTec''': The HighTec compiler is a popular choice, known for its Eclipse-based development environment and strong multicore support. HighTec provides both GCC and LLVM-based ports of open-source compilers tailored specifically for the AURIX TC3xx family. These compilers offer efficient parallel execution, advanced code analysis, and an integrated development environment, ensuring robust performance and compliance with safety standards.
# '''Green Hills Software''': Green Hills Software provides a highly optimized toolchain aimed at safety-critical applications, focusing on high performance and strict compliance with automotive standards. Their compiler offers superior optimization, extensive safety features, and a proprietary IDE with specialized tools for automotive development, ensuring developers can meet the stringent demands of functional safety.

=== GCC for AURIX ===

While mainline GCC does not directly support the AURIX TC3xx family, there is an unofficial GCC version available for AURIX. Due to the GNU General Public License (GPL), the source code from HighTec was retrieved and, along with binary versions, published on GitHub:

*GCC 4.9.4/Binutils 2.20/Newlib 1.18 for Tricore Aurix [[https://github.com/volumit/package_494 Source]] [[https://github.com/volumit/tricore_gcc494_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc494_linux_bins Prebuild Linux Binaries]]
*GCC 9.4.0/Binutils 2.20/Newlib 1.18 for Tricore Aurix [[https://github.com/volumit/package_940 Source]] [[https://github.com/volumit/tricore_gcc940_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc940_linux_bins Prebuild Linux Binaries]]
*GDB 10.0.50 for Tricore Aurix [[https://github.com/volumit/gdb-tricore Source]]
==emmtrix Tools for AURIX TC3xx==
emmtrix offers the following tool for the Infineon AURIX TC3xx architecture:
*[https://www.emmtrix.com/tools/emmtrix-performance-estimatorator emmtrix Performance Estimator] for estimating the performance of C code written for the Tricore CPUs.

=== emmtrix Performance Estimator ===
[https://www.emmtrix.com/tools/emmtrix-performance-estimator emmtrix Performance Estimator (ePE)] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ TC2xx / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

We provide our tools with all required services (training, consulting, customization).

=== Services ===

=== Associated Partnership ===
[[File:lowres-Signet Associated Partner EN.eps.png|left|thumb|204x204px|Infineon Associated Partnership]]
emmtrix Technologies has over 10 years of experience working with Infineon and their '''AURIX™ microcontroller family''' and has been collaborating for the past five years.

Our tools enable precise performance estimation, automated vectorization, and multi-core optimization, including support for the latest '''AURIX™ TC4x''' generation.

==See Also==

*[[Infineon AURIX TC4x]]
*[[TriCore Instruction Set Architecture]]

==External Links==

*https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/
*[https://documentation.infineon.com/aurixtc3xx/docs/qmd1702366622648 AURIX TC3xx user manuals]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d3605221d96 AURIX™ TC3xx User Manual Part-1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d35f8541d94 AURIX™ TC3xx User Manual Part-2]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd AURIX™ TC3xx Architecture vol 1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 AURIX™ TC3xx Architecture vol 2]

[[Category:Supported Architectures]]

Infineon AURIX TC3xx

2025-03-20T12:53:40Z

Mira.steinmetz:

File:lowres-Signet Associated Partner EN.eps.png

2025-03-20T12:17:55Z

Mira.steinmetz:

Infineon AURIX TC3xx

2025-03-20T12:16:34Z

Mira.steinmetz:

== Architecture ==
[[File:Infineon TC3xx Architecture.webp|center|frameless|844x844px]]

=== On-Chip System Connectivity and Bridges ===
[[File:TC3xx On-Chip System Connectivity.png|thumb|SRI Domains]]
The AURIX™ TC3xx Platform has three independent on-chip connectivity resources:

* '''System Resource Interconnect Fabric (SRI Fabric)''' connects the TriCore CPUs, the DMA module, and other high bandwidth requestors to high bandwidth memories and other resources for instruction fetches and data accesses. A key component of the fabric is the SRI crossbar, which connects all the agents in one SRI domain. The SRI crossbar carries the transactions between the SRI Masters and SRI Slaves of the domain. The SRI crossbar supports parallel transactions between different SRI Master and SRI Slave agents. In addition to the parallelism of concurrent requests, it also supports pipelined requests from an SRI Master to a SRI Slave.
* '''System Peripheral Bus (SPB)''' connects the TriCore CPUs, the DMA module, and other SPB masters to the medium and low bandwidth peripherals. SPB masters do not directly connect to the SRI Fabric, and will access SRI attached resources via a SFI_F2S Bridge.
* '''Back Bone Bus (BBB)''' connects the TriCore CPUs, the DMA module, and SPB masters with ADAS resources. SRI Masters do not directly connect to the BBB, but access BBB attached resources via a SFI_S2F Bridge. SPB masters also do not directly connect to the BBB, but access BBB attached resources via bridging over the SRI Fabric.

=== CPU Resource Access Times ===
These tables describe the CPU access times to various resources in CPU clock cycles for the AURIX™ TC3xx Platform. In the case of load or fetch accesses, the access times are the minimum number of CPU stall cycles to complete the access. If there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

For write access, the access times are the maximum for a sequence of such access (non-conflicting). In many cases for a singleton access, or a short sequence, write buffering reduces the stall effect seen by a CPU, sometimes to 0. However, as with loads and fetches, if there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

==== Access latency for global resources ====
{| class="wikitable"
|+
! CPU Access Type !! CPU stall cycles
!Notes
|-
| Data read from System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
| rowspan="2" |The final number of stall cycles will depend on the real number of WS generated by the target resource.
|-
| Data write to System Peripheral Bus (SPB) || <math>\frac{f_\text{CPU}}{f_\text{SPB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC39x, TC37xED) || <math>9 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
| rowspan="2" |When SFI_S2F is connected to XBar2 (TC39x and TC37xED) there is an additional latency due to access going through an S2S.
|-
| Data write to Back Bone Bus (BBB) (TC39x, TC37xED) || <math>5 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|-
| Data read from Back Bone Bus (BBB) (TC35x, TC33xED) || <math>6 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (5 + \text{Module Wait State})</math>
|
|-
| Data write to Back Bone Bus (BBB) (TC35x, TC33xED) || <math>3 + \frac{f_\text{CPU}}{f_\text{BBB}} \cdot (4 + \text{Module Wait State})</math>
|
|}


* '''Module Wait State''': The number of wait states for read and for write accesses is >= 1 and depends on the accessed module and its configuration.


==== CPU Accesses: Stall cycles for local and SRI resources ====
{| class="wikitable"
|+
! CPU Access Type !! Local CPU !! Local SRI !! Remote SRI Domain
|-
| Data read from DSPR || 0 || 7 || 10
|-
| Data write to DSPR || 0 || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from DSPR || See local SRI column || 7 || 10
|-
| Data read from DLMU || 0 || 7 || 10
|-
| Data write to DLMU || 2 || 5, {{rev|3|with Pipelining}}|| 5, 4
|-
| Instruction fetch from DLMU || See local SRI column || 7 || 10
|-
| Data read from PSPR || See local SRI column || 7 || 10
|-
| Data write to PSPR || See local SRI column || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from PSPR || 0 || 7 || 10
|-
| Data read from PFlash || 5 + PWS || 10 + PWS || 13 + PWS
|-
| Instruction fetch from PFlash (buffer miss) || 2 + PWS || 9 + PWS || 12 + PWS
|-
| Instruction fetch from PFlash (buffer hit) || 3 || 6 || 9
|-
| Data read from LMU || n.a. || 7 || 10
|-
| Data write to LMU || n.a. || 5, {{rev|3|with Pipelining}}|| 5, {{rev|4|with Pipelining}}
|-
| Instruction fetch from LMU || n.a. || 7 || 10
|-
| Data read from DFlash || n.a. || 5 + 3*(3 + DCWS) || 8 + 3*(3 + DCWS)
|-
| Data read access from EMEM (TC39x, TC37xED) || n.a. || n.a. || 14, {{rev|15|fBBB < fSRI}}
|-
| Data write access to EMEM (TC39x, TC37xED) || n.a. || n.a. || 9
|-
| Data read access from EMEM (TC35x, TC33xED) || n.a. || 11, {{rev|12|fBBB < fSRI}}|| n.a.
|-
| Data write access to EMEM (TC35x, TC33xED) || n.a. || 9 || n.a.
|-
| Data read access from DAM || n.a. || 10 || 13
|-
| Data write access to DAM || n.a. || 7 || 7
|}

* '''Remote SRI Domain''': Only applies to products with SRI extenders. Additional latency due to access going through an S2S
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''PWS''': Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
* '''DCWS''': Configured DFlash Corrected Wait States (Includes cycles for DFlash access cycles and ECC correction latency)

== CPU Subsystem (CPU0 ... CPU5) ==
[[File:TC3xx Processor Core, Local Memory and Connectivity.png|alt=TC3xx Processor Core, Local Memory and Connectivity|thumb|Processor Core, Local Memory and Connectivity]]The Infineon AURIX TC3xx features up to 6 processor cores implementing the [[Tricore TC1.6.2 Instruction Set Architecture|TC1.6.2 instruction set architecture]]. The following section focuses on the microarchitectural details of the CPU subsystem. For more information about the ISA, please take a look at the [[Tricore Instruction Set Architecture|TC1.6.2 article]].

The processor core connects to the following memories and bus interfaces (where implemented):
*Program Scratch-Pad SRAM (PSPR)
*Data Scratch-Pad SRAM (DSPR)
*Program Cache (PCache)
*Data Cache (DCache)
*Local Memory Unit (DLMU)
*Local Pflash bank (LPB)
*SRI slave interface (x2)
*SRI master Interface
*SPB master interface

=== TC1.6.2P Implementation Features ===
*Most instructions executed in 1 cycle
*Branch instructions in 1, 2 or 3 cycles (using dynamic branch prediction)
*Wide memory interface for fast context switch
* Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
*Six memory protection register sets
*Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
*Third pipeline for loop instruction only (zero overhead loop)
*Single precision Floating Point Unit (IEEE-754 Compatible)
*Dedicated Integer divide unit
*18 data memory protection ranges, 10 code memory protection ranges arranged in 6 sets

=== Pipeline ===

=== Instruction Timing ===

== Platform Devices ==
The following table shows a feature overview of the AURIX™ TC3xx Platform family focusing on memory and number of cores.
{| class="wikitable"
!
!Feature
!TC33x
!TC33xEXT
!TC35x
!TC36x
!TC37x
!TC37xEXT
!TC38x
!TC39x
|-
| rowspan="2" |CPUs
|Cores / Checker Cores
|1 / 1
|2 / 1
|3 / 2
|2 / 2
|3 / 2
|3 / 3
|4 / 2
|6 / 4
|-
|Max. Freq.
| colspan="8" |300 MHz
|-
| rowspan="2" |Cache per CPU
|Program [KB]
| colspan="8" |32
|-
|Data [KB]
| colspan="8" |16
|-
| rowspan="3" |SRAM per CPU
|PSPR [KB]
|8
|{{rev|32|CPU0}}
{{rev|64|other}}
|64
|32
|64
|64
|64
|64
|-
|DSPR [KB]
|192
|{{rev|192|CPU0}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|192
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|{{rev|240|CPU0&1}}
{{rev|64|other}}
|-
|DLMU [KB]
|8
|{{rev|8|CPU0}}
{{rev|64|other}}
|64
|64
|64
|64
|64
|64
|-
| rowspan="2" |SRAM global
|LMU [KB]
| -
| -
|512
| -
| -
| -
|128
|768
|-
|DAM [KB]
| -
| -
|32
| -
|64
|64
|128
|128
|-
| rowspan="3" |Extension Memory (EMEM)
|TCM [MB]
| -
|1
|2
| -
| -
|2
| -
|2
|-
|XCM [MB]
| -
| -
| -
| -
| -
|1
| -
|2
|-
|XTM [KB]
| -
|16
|16
| -
| -
|16
| -
|16
|-
| rowspan="2" |Program Flash
|Size [MB]
|2
|4
|4
|4
|6
|10
|10
|16
|-
|Banks [MB]
|1 x 2
|2 x 2
|2 x 2
|2 x 2
|2 x 3
|3 x 3, 1 x 1
|3 x 3, 1 x 1
|5 x 3, 1 x 1
|-
| rowspan="2" |Data Flash
|DF0 Size (single-ended) [KB]
|128
|128
|128
|128
|256
|512
|512
|1024
|-
|DF1 Size (single-ended) [KB]
|128
|128
|128
|128
|128
|128
|128
|128
|-
| rowspan="3" |DMA
|Channels
|64
|64
|64
|64
|128
|128
|128
|128
|-
|Move Engines
|2
|2
|2
|2
|2
|2
|2
|2
|-
|Resource Partitions
|4
|4
|4
|4
|4
|4
|4
|4
|}

== Compilers ==
The AURIX TC3xx family is a series of high-performance microcontrollers widely used in automotive and industrial applications. Compilers for the AURIX TC3xx are crucial for developers aiming to optimize performance, reliability, and safety in their applications. One significant aspect of the compiler landscape for AURIX TC3xx is the limited direct support from mainline open-source compilers such as GCC or LLVM/Clang. The primary reason for this is the stringent requirements for functional safety in automotive and industrial applications, which demand specialized features and compliance with safety standards that are often not met by general-purpose open-source compilers.

=== Commercial Compilers ===

# '''Tasking''': Tasking compilers are renowned for their robust support for automotive applications, offering advanced debugging capabilities and optimization techniques tailored for the AURIX architecture. They provide extensive code optimization, comprehensive debugging tools, and strong support for safety standards such as ISO 26262, making them ideal for developing high-performance, reliable, and safe applications.
# '''HighTec''': The HighTec compiler is a popular choice, known for its Eclipse-based development environment and strong multicore support. HighTec provides both GCC and LLVM-based ports of open-source compilers tailored specifically for the AURIX TC3xx family. These compilers offer efficient parallel execution, advanced code analysis, and an integrated development environment, ensuring robust performance and compliance with safety standards.
# '''Green Hills Software''': Green Hills Software provides a highly optimized toolchain aimed at safety-critical applications, focusing on high performance and strict compliance with automotive standards. Their compiler offers superior optimization, extensive safety features, and a proprietary IDE with specialized tools for automotive development, ensuring developers can meet the stringent demands of functional safety.

=== GCC for AURIX ===

While mainline GCC does not directly support the AURIX TC3xx family, there is an unofficial GCC version available for AURIX. Due to the GNU General Public License (GPL), the source code from HighTec was retrieved and, along with binary versions, published on GitHub:

*GCC 4.9.4/Binutils 2.20/Newlib 1.18 for Tricore Aurix [[https://github.com/volumit/package_494 Source]] [[https://github.com/volumit/tricore_gcc494_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc494_linux_bins Prebuild Linux Binaries]]
*GCC 9.4.0/Binutils 2.20/Newlib 1.18 for Tricore Aurix [[https://github.com/volumit/package_940 Source]] [[https://github.com/volumit/tricore_gcc940_mingw_bins Prebuild Mingw Binaries]] [[https://github.com/volumit/tricore_gcc940_linux_bins Prebuild Linux Binaries]]
*GDB 10.0.50 for Tricore Aurix [[https://github.com/volumit/gdb-tricore Source]]
==emmtrix Tools for AURIX TC3xx==
emmtrix offers the following tool for the Infineon AURIX TC3xx architecture:
*[https://www.emmtrix.com/tools/emmtrix-performance-estimatorator emmtrix Performance Estimator] for estimating the performance of C code written for the Tricore CPUs.

=== emmtrix Performance Estimator ===
[https://www.emmtrix.com/tools/emmtrix-performance-estimator emmtrix Performance Estimator (ePE)] provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program.

ePE offers three accuracy levels:

* analysis of C code
* generically compiler-optimized code
* assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

emmtrix Performance Estimator is fully compatible with '''Infineon's AURIX™ TC2xx / TC3xx/ [[Infineon AURIX TC4x|TC4x]] microcontroller family,''' ensuring precise and reliable performance analysis for embedded systems.

We provide our tools with all required services (training, consulting, customization).

=== Services ===

=== Associated Partnership ===

==See Also==

*[[Infineon AURIX TC4x]]
*[[TriCore Instruction Set Architecture]]

==External Links==

*https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/
*[https://documentation.infineon.com/aurixtc3xx/docs/qmd1702366622648 AURIX TC3xx user manuals]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d3605221d96 AURIX™ TC3xx User Manual Part-1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Part2-UserManual-v02_00-EN.pdf?fileId=5546d462712ef9b701717d35f8541d94 AURIX™ TC3xx User Manual Part-2]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4c2e33bdd AURIX™ TC3xx Architecture vol 1]
**[https://www.infineon.com/dgdl/Infineon-AURIX_TC3xx_Architecture_vol2-UserManual-v01_00-EN.pdf?fileId=5546d46276fb756a01771bc4a6d73b70 AURIX™ TC3xx Architecture vol 2]

[[Category:Supported Architectures]]

Loop Invariant Code Motion

2025-02-17T10:06:49Z

Mira.steinmetz: Created page with "Loop invariant code motion is an optimization technique that moves computations outside of a loop if they do not depend on the loop iterator. By extracting such invariant expressions, this transformation reduces redundant calculations and improves runtime efficiency. It minimizes unnecessary operations within loops, leading to faster execution and better performance. This technique is particularly useful in optimizing complex loops, reducing computation overhead, and ena..."

Loop invariant code motion is an optimization technique that moves computations outside of a loop if they do not depend on the loop iterator. By extracting such invariant expressions, this transformation reduces redundant calculations and improves runtime efficiency. It minimizes unnecessary operations within loops, leading to faster execution and better performance. This technique is particularly useful in optimizing complex loops, reducing computation overhead, and enabling further compiler optimizations.
==Loop Invariant Code Motion Transformation in emmtrix Studio==
emmtrix Studio implements loop invariant code motion using #pragma directives or via the GUI. Loop invariant code motion is a transformation that moves code that is invariant from the loop iterator in front of the loop.
===Typical Usage and Benefits===
Loop invariant code motion is typically used to improve the runtime of an application by moving loop invariant parts out of loops in order to reduce the number of times they are executed.
===Example===
{| class="wikitable"
|-
|<syntaxhighlight lang="c">
/* The following code tests loop invariant code motion transformation applied to a for loop: */

int main(void) {
#pragma EMX_TRANSFORMATION LoopInvariantCodeMotion
for (int i = 0; i < 10; ++i) {
int inv = 10;
int inv2 = inv * inv;
printf(” % d\ n”, inv2);
}
return 0
}
</syntaxhighlight>
|<syntaxhighlight lang="c">
/* The generated code: */

int main(void) {
int inv = 10;
int inv2 = inv * inv;
for (int i = 0; i < 10; ++i) {
printf(” % d\ n”, inv2);
}
return 0;
}
</syntaxhighlight>
|}
===Parameters===
Following parameters can be set (each description is followed by keyword in pragma-syntax and default value):
{| class="wikitable"
|+
!Id
!Default Value
!Description
|-
|<code>subExprs</code>
|false
|'''Move sub-expressions by creating temporary variables''' - move expressions that require the insertion of temporary variables in order to make the code more efficient
|-
|<code>reorderInvExprs</code>
|false
|'''Reorder invariant expressions by applying the commutative and associative laws''' - enables reordering of moved expressions that allows more optimizations for better efficiency
|-
|<code>xpectedMovedExpr</code>
| -1
|'''Expected moved expressions''' - can be used for testing purposes by inserting the number of expected moved expressions. Creates an error if the numbers differ, does nothing when set to -1
|}

=== Note ===

* To move functions from math.h, use the [[Idiom Recognizer|idiom recognizer]] transformation to identify the functions and apply the code sinking transformation afterwards.

[[Category:Code Transformation]]

While To For

2025-02-17T09:49:06Z

Mira.steinmetz: Created page with "The while-to-for transformation converts a selected while loop into an equivalent for loop while preserving the original loop semantics. This conversion improves code consistency and enables further compiler optimizations that specifically target for-loop structures. By restructuring loops in a standardized format, this transformation facilitates better loop analysis, enhances readability, and increases the potential for optimizations such as loop unrolling or vectorizat..."

The while-to-for transformation converts a selected while loop into an equivalent for loop while preserving the original loop semantics. This conversion improves code consistency and enables further compiler optimizations that specifically target for-loop structures. By restructuring loops in a standardized format, this transformation facilitates better loop analysis, enhances readability, and increases the potential for optimizations such as loop unrolling or vectorization.
==While-to-for Transformation in emmtrix Studio==
emmtrix Studio implements while-to-for using #pragma directives or via the GUI. While-to-for is a transformation that replaces selected while block with a for block of the same semantics.
===Typical Usage and Benefits===
While-ro-for is typically used to allow other for-loop-based transformations and analysis to be performed.
===Example===
{| class="wikitable"
|-
|<syntaxhighlight lang="c">
/* The following code tests while-to-for transformation applied to a for loop: */

int main(void) {
int sum = 0;
int i = 0;
#pragma EMX_TRANSFORMATION WhileToFor
while (i < 10) {
sum += i;
i++;
}
return 0;
}
</syntaxhighlight>
|<syntaxhighlight lang="c">
/* The generated code:*/

int main(void) {
int sum = 0;
int i;
for (i = 0; i < 10; i = i + 1) {
sum += i;
}
return 0;
}
</syntaxhighlight>
|}
[[Category:Code Transformation]]

Loop Interchange Transformation

2025-02-17T09:41:37Z

Mira.steinmetz: Created page with "Loop interchange is an optimization technique that swaps the order of nested loops, making the inner loop the outer loop and vice versa. This transformation can improve data locality, optimize memory access patterns, and expose opportunities for parallelization and vectorization. By reordering loops, loop interchange can enhance cache efficiency and reduce execution time, especially in matrix operations or scenarios where data access patterns impact performance. It is pa..."

Loop interchange is an optimization technique that swaps the order of nested loops, making the inner loop the outer loop and vice versa. This transformation can improve data locality, optimize memory access patterns, and expose opportunities for parallelization and vectorization. By reordering loops, loop interchange can enhance cache efficiency and reduce execution time, especially in matrix operations or scenarios where data access patterns impact performance. It is particularly useful in optimizing code for modern processors and parallel computing architectures.
==Loop Interchange Transformation in emmtrix Studio==
emmtrix Studio implements loop interchange using #pragma directives or via the GUI. Loop interchange is a transformation that swaps two nested loops with each other, so that the inner loop becomes the outer one and vice versa.
===Typical Usage and Benefits===
Loop interchange is used to change granularity of the outer loops which has parallelization implications. Another important application of loop interchange is in scenarios in which vectorization possibilities could be exposed. By interchanging the loops some previously scattered data elements could now be localized.
===Example===
{| class="wikitable"
|-
|<syntaxhighlight lang="c">
/* The following code tests loop interchange transformation applied to a for loop: */

#define N 5
int main(void) {
int i1, i2;
int a[N][N] = { 0 };
#pragma EMX_TRANSFORMATION LoopInterchange
for (i1 = 0; i1 < N; i1++) {
for (i2 = 0; i2 < N; i2++) {
a[i1][i2] = a[i1][i2] + 5;
}
}
return 0;
}
</syntaxhighlight>
|<syntaxhighlight lang="c">
/* The generated code:*/

int main(void) {
int i1 ;
int i2 ;
int a [5][5] = {0};
for (i2 = 0; i2 < 5; i2 = i2 + 1) {
for (i1 = 0; i1 < 5; i1 = i1 + 1) {
a[i1 ][ i2 ] = a[i1 ][ i2 ] + 5;
}
}
return 0;
}
</syntaxhighlight>
|}
[[Category:Code Transformation]]

Loop Unrolling Transformation

2025-02-17T09:33:09Z

Mira.steinmetz:

Loop unrolling is an optimization technique that reduces the number of iterations in a loop by expanding its body to process multiple elements per iteration. This transformation decreases loop overhead, improves execution efficiency, and can enhance opportunities for parallelization. By reducing control flow instructions, loop unrolling minimizes branching and increases instruction-level parallelism, making it particularly useful for performance-critical applications. While it can lead to larger code size, the trade-off often results in significant runtime improvements.
==Loop Unrolling Transformation in emmtrix Studio==
emmtrix Studio implements loop unrolling using #pragma directives or via the GUI. Unrolling will reduce the iteration count and increase the body of the loop, processing statements from multiple iteration steps in a single iteration.
===Typical Usage and Benefits===
Loop unrolling is used to reduce the overhead of the loops and to exploit parallelization on coarser parts.
===Example===
{| class="wikitable"
|-
|<syntaxhighlight lang="c">
/* The following code tests loop unroll transformation applied to a for loop: */

int main(void) {
int i;
int a[4];
#pragma EMX_TRANSFORMATION LoopUnroll { ”unrollfactor”: 4}
for (i = 0; i < 4; i++) {
a[i] = i;
}
return 0;
}
</syntaxhighlight>
|<syntaxhighlight lang="c">
/* The generated code includes all four iterations of the loop transformed into four separate statements.
* The loop unrolling is full and the loop is removed.
*/

int main(void) {
int i;
int a[4];
i = 0;
{
a[i] = i;
} {
a[i + 1 * 1] = i + 1 * 1;
} {
a[i + 1 * 2] = i + 1 * 2;
} {
a[i + 1 * 3] = i + 1 * 3;
}
return 0;
}
</syntaxhighlight>
|}
===Parameters===
Following parameters can be set (each description is followed by keyword in pragma-syntax and default value):
{| class="wikitable"
|+
!Id
!Default Value
!Description
|-
|<code>unrollfactor</code>
|max_unrollfactor
|'''Unroll factor''' - divide iteration count & multiply iterating variable. If equal to total number of iterations, loop-construct will be removed from code. If not integer divisor of total number of iterations, additional loop
processing last iterations will be added
|}
[[Category:Code Transformation]]

Loop Fission

2025-02-17T09:32:29Z

Mira.steinmetz:

Loop fission, also known as loop distribution, is an optimization technique that splits a single loop into multiple loops over the same iteration range, with each handling a subset of the original loop’s operations. This transformation improves data locality, enhances cache efficiency, and enables better parallelization by reducing dependencies within a loop body. By breaking down complex loops, loop fission can optimize memory access patterns and improve overall program performance while preserving the original computation logic.
==Loop Fission Transformation in emmtrix Studio==
emmtrix Studio implements loop fission using #pragma directives or via the GUI. Loop fission is a transformation that breaks a loop into multiple loops over the same index range with each taking only a part of the original loop’s body.
===Typical Usage and Benefits===
Loop fission is used to achieve better utilization of locality of reference by breaking down a large loop body into smaller ones.
===Example===
{| class="wikitable"
|-
|<syntaxhighlight lang="c">
/* The following code tests loop fission transformation applied to a for loop: */

int main() {
int i, j;
int a[10], b, c, d;
#pragma EMX_TRANSFORMATION LoopFission
for (i = 0; i < 10; i++) {
d = 0;
a[i] = i * i;
c = 9;
b = i;
b = 8 + i * b;
if (a[i] > 50) {
c = c + a[i];
printf(”Inside
if, a[ % d] = % d and c = % d\ n”, i, a[i], c);
} else {
printf(”Inside
else, c = % d\ n”, c);
printf(”Inside
else, a[ % d] = % d\ n”, i, a[i]);
}
}
}
</syntaxhighlight>
|<syntaxhighlight lang="c">
/* The generated code has multiple loops, each loop containing groups of statements from the old loop
that have dependencies on one another: */

int main() {
int i;
int j;
int a[10];
int b;
int c;
int d;
{
for (i = 0; i < 10; i = i + 1) {
d = 0;
}
for (i = 0; i < 10; i = i + 1) {
a[i] = i * i;
c = 9;
if (a[i] > 50) {
c = c + a[i];
printf(”Inside
if, a[ % d] = % d and c = % d\ n”, i, a[i], c);
} else {
printf(”Inside
else, c = % d\ n”, c);
printf(”Inside
else, a[ % d] = % d\ n”, i, a[i]);
}
}
for (i = 0; i < 10; i = i + 1) {
b = i;
b = 8 + i * b;
}
}
}
</syntaxhighlight>
|}
[[Category:Code Transformation]]

Loop If-Split

2025-02-17T09:31:44Z

Mira.steinmetz: Created page with "If-split is an optimization technique that restructures loop-nested if-else statements by transforming them into separate independent loops. This transformation simplifies control flow, making data dependency analysis more efficient and increasing the potential for parallel execution. By eliminating branching within a loop, if-split enhances performance, particularly in scenarios where different execution paths can be processed independently. This technique is especially..."

If-split is an optimization technique that restructures loop-nested if-else statements by transforming them into separate independent loops. This transformation simplifies control flow, making data dependency analysis more efficient and increasing the potential for parallel execution. By eliminating branching within a loop, if-split enhances performance, particularly in scenarios where different execution paths can be processed independently. This technique is especially useful in optimizing loops for better hardware utilization and improved computational efficiency.
==Loop If-Split Transformation in emmtrix Studio==
emmtrix Studio implements loop if-split using #pragma directives or via the GUI. If-split is a transformation that splits loop-nested if-else statements into independent loops. The transformation can be applied only on if-else statements with different paths.
===Typical Usage and Benefits===
If-split is used to simplify data dependency analysis by generating less complex control-flow graphs. If-split increases potential for parallel execution.
===Example===
{| class="wikitable"
|-
|<syntaxhighlight lang="c">
/* The following code tests loop if-split transformation applied to a for loop: */

#include <stdio.h>
int main(void) {
#pragma EMX_TRANSFORMATION IfSplit
for (j = 0; j < 8; j++) {
if (j < 4) {
suma += a[j];
} else {
sumb += b[j];
}
}
return 0;
}
</syntaxhighlight>
|<syntaxhighlight lang="c">
/* The generated code includes two loops, one separate loop for each of the original loop body state-
ments: */

#include <stdio.h>

int main(void) {
for (j = 0; j < 4; j = j + 1) {
{
suma = suma + a[j];
}
}
for (j = 4; j < 8; j = j + 1) {
{
sumb = sumb + b[j];
}
}
return 0;
}
</syntaxhighlight>
|}
[[Category:Code Transformation]]

Loop Fission

2025-02-17T09:22:34Z

Mira.steinmetz:

Loop fission, also known as loop distribution, is an optimization technique that splits a single loop into multiple loops over the same iteration range, with each handling a subset of the original loop’s operations. This transformation improves data locality, enhances cache efficiency, and enables better parallelization by reducing dependencies within a loop body. By breaking down complex loops, loop fission can optimize memory access patterns and improve overall program performance while preserving the original computation logic.
==Loop Fission Transformation in emmtrix Studio==
emmtrix Studio implements loop fission using #pragma directives or via the GUI. Loop fission is a transformation that breaks a loop into multiple loops over the same index range with each taking only a part of the original loop’s body.
===Typical Usage and Benefits===
Loop fission is used to achieve better utilization of locality of reference by breaking down a large loop body into smaller ones.
===Example===
{| class="wikitable"
|-
|<syntaxhighlight lang="c">
/* The following code tests LoopUnroll transformation applied to a for loop: */

int main() {
int i, j;
int a[10], b, c, d;
#pragma EMX_TRANSFORMATION LoopFission
for (i = 0; i < 10; i++) {
d = 0;
a[i] = i * i;
c = 9;
b = i;
b = 8 + i * b;
if (a[i] > 50) {
c = c + a[i];
printf(”Inside
if, a[ % d] = % d and c = % d\ n”, i, a[i], c);
} else {
printf(”Inside
else, c = % d\ n”, c);
printf(”Inside
else, a[ % d] = % d\ n”, i, a[i]);
}
}
}
</syntaxhighlight>
|<syntaxhighlight lang="c">
/* The generated code has multiple loops, each loop containing groups of statements from the old loop
that have dependencies on one another: */

int main() {
int i;
int j;
int a[10];
int b;
int c;
int d;
{
for (i = 0; i < 10; i = i + 1) {
d = 0;
}
for (i = 0; i < 10; i = i + 1) {
a[i] = i * i;
c = 9;
if (a[i] > 50) {
c = c + a[i];
printf(”Inside
if, a[ % d] = % d and c = % d\ n”, i, a[i], c);
} else {
printf(”Inside
else, c = % d\ n”, c);
printf(”Inside
else, a[ % d] = % d\ n”, i, a[i]);
}
}
for (i = 0; i < 10; i = i + 1) {
b = i;
b = 8 + i * b;
}
}
}
</syntaxhighlight>
|}
[[Category:Code Transformation]]

Loop Fission

2025-02-17T09:15:23Z

Mira.steinmetz: Created page with "Loop unrolling is an optimization technique that reduces the number of iterations in a loop by expanding its body to process multiple elements per iteration. This transformation decreases loop overhead, improves execution efficiency, and can enhance opportunities for parallelization. By reducing control flow instructions, loop unrolling minimizes branching and increases instruction-level parallelism, making it particularly useful for performance-critical applications. Wh..."

Loop unrolling is an optimization technique that reduces the number of iterations in a loop by expanding its body to process multiple elements per iteration. This transformation decreases loop overhead, improves execution efficiency, and can enhance opportunities for parallelization. By reducing control flow instructions, loop unrolling minimizes branching and increases instruction-level parallelism, making it particularly useful for performance-critical applications. While it can lead to larger code size, the trade-off often results in significant runtime improvements.
==Loop Unrolling Transformation in emmtrix Studio==
emmtrix Studio implements loop unrolling using #pragma directives or via the GUI. Unrolling will reduce the iteration count and increase the body of the loop, processing statements from multiple iteration steps in a single iteration.
===Typical Usage and Benefits===
Loop unrolling is used to reduce the overhead of the loops and to exploit parallelization on coarser parts.
===Example===
{| class="wikitable"
|-
|<syntaxhighlight lang="c">
/* The following code tests LoopUnroll transformation applied to a for loop: */

int main(void) {
int i;
int a[4];
#pragma EMX_TRANSFORMATION LoopUnroll { ”unrollfactor”: 4}
for (i = 0; i < 4; i++) {
a[i] = i;
}
return 0;
}
</syntaxhighlight>
|<syntaxhighlight lang="c">
/* The generated code includes all four iterations of the loop transformed into four separate statements.
* The loop unrolling is full and the loop is removed.
*/

int main(void) {
int i;
int a[4];
i = 0;
{
a[i] = i;
} {
a[i + 1 * 1] = i + 1 * 1;
} {
a[i + 1 * 2] = i + 1 * 2;
} {
a[i + 1 * 3] = i + 1 * 3;
}
return 0;
}
</syntaxhighlight>
|}
===Parameters===
Following parameters can be set (each description is followed by keyword in pragma-syntax and default value):
{| class="wikitable"
|+
!Id
!Default Value
!Description
|-
|<code>unrollfactor</code>
|max_unrollfactor
|'''Unroll factor''' - divide iteration count & multiply iterating variable. If equal to total number of iterations, loop-construct will be removed from code. If not integer divisor of total number of iterations, additional loop
processing last iterations will be added
|}