New pages
Jump to navigation
Jump to search
- 12:08, 21 November 2024 ULP Difference of Float Numbers (hist | edit) [15,016 bytes] Timo.stripf (talk | contribs) (Created page with "'''Unit in the Last Place (ULP)''' is a term used in computing to describe the difference in representation between two floating-point numbers. It is the smallest possible difference between two distinct floating-point values at a given precision. In simpler terms, ULP helps measure how many discrete steps separate two floating-point numbers, which is particularly useful when assessing rounding errors and numerical stability in floating-point computations. In floating-p...") Tag: Visual edit
- 13:47, 15 November 2024 tanh Software Implementation (hist | edit) [42,723 bytes] Timo.stripf (talk | contribs) (Created page with " {{#widget:TestGoogleGraph |data=[["-2^127",0,0],["-2^126",0,0],["-2^125",0,0],["-2^124",0,0],["-2^123",0,0],["-2^122",0,0],["-2^121",0,0],["-2^120",0,0],["-2^119",0,0],["-2^118",0,0],["-2^117",0,0],["-2^116",0,0],["-2^115",0,0],["-2^114",0,0],["-2^113",0,0],["-2^112",0,0],["-2^111",0,0],["-2^110",0,0],["-2^109",0,0],["-2^108",0,0],["-2^107",0,0],["-2^106",0,0],["-2^105",0,0],["-2^104",0,0],["-2^103",0,0],["-2^102",0,0],["-2^101",0,0],["-2^100",0,0],["-2^99",0,0],["-2...") Tag: Visual edit: Switched
- 22:49, 13 October 2024 Infineon AURIX TC2xx (hist | edit) [314 bytes] Timo.stripf (talk | contribs) (Created page with "== External Links == * https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc2xx/ * [https://www.infineon.com/dgdl/Infineon-TC29x_B-step-UM-v01_03-EN.pdf?fileId=5546d46269bda8df0169ca1bdee424a2 TC29x B-Step User Manual] Category:Supported Architectures") Tag: Visual edit
- 08:01, 11 October 2024 TriCore Instruction Set Architecture (hist | edit) [30,097 bytes] Timo.stripf (talk | contribs) (Created page with "TriCore is a unified, 32-bit microcontroller-DSP, single-core architecture optimized for real-time embedded systems. == Features == The key features of the TriCore Instruction Set Architecture (ISA) are: * • 32-bit architecture * • 4 GBytes of address space * • 16-bit and 32-bit instructions for reduced code size * • Most instructions executed in one cycle * • Branch instructions (using branch prediction) * • Low interrupt latency with fast automatic contex...") Tag: Visual edit originally created as "Tricore TC1.6.2 Instruction Set Architecture"
- 08:55, 30 September 2024 emmtrix Code Generator (hist | edit) [4,403 bytes] Mira.steinmetz (talk | contribs) (Created page with "== Our Solution for MATLAB® Code Generation == emmtrix Code Generator (eCG) translated MATLAB®, GNU Octave, or Scilab code into platform-independent and readable C or C++ code suitable for embedded processors. The generated code was easy to understand, prepared for parallelization, and could be adjusted to individual requirements. Automatically generated reports helped with the code certification process. In combination with emmtrix Parallel Studio, eCG enabled multico...") Tag: Visual edit
- 08:10, 30 September 2024 emmtrix Model Code Generator (hist | edit) [1,943 bytes] Mira.steinmetz (talk | contribs) (Created page with "== Our Solution for Simulink® == The emmtrix Model Code Generator translated your Simulink® models (''.slx) into MATLAB® or GNU Octave script files (''.m). The generated code was easy to understand and provided traceability to the original Simulink® blocks. If you wanted to convert your *.m files to C or C++, you could use our emmtrix Code Generator to complete the entire process in one tool.") Tag: Visual edit
- 09:05, 27 September 2024 Logical Execution Time (LET) (hist | edit) [4,976 bytes] Mira.steinmetz (talk | contribs) (Created page with "Logical Execution Time for Control Applications The most obvious approach for parallelization or porting control software to multi-core systems is based on a last is best model that relies on shared memory and global variables. However, jitter can occur when using this approach, which results in non-deterministic runtime behaviour. Additionally, the approach has poor scalability with the number of cores. This article discusses the use of logical execution time for paral...")