Talk:Infineon AURIX TC4x Parallel Processing Unit (PPU)

512-bit PPU

The bit-width of the PPU is not fixed to 512-bit. It is flexible between 128 and 256-bits.

Rework toolchain chapter

The toolchain chapter is tool Synopsys centric. It needs rework.

Programming Model and Toolchain Support

Programming the AURIX TC4x’s PPU requires a toolchain that can generate code for the Synopsys ARC EV71 vector architecture and integrate it with the rest of the microcontroller’s software. Infineon, in collaboration with Synopsys and ecosystem partners, provides a comprehensive set of development tools for the PPU. The Synopsys ARC MetaWare Toolkit for AURIX TC4x is a primary offering, which includes compilers, libraries, and debugging support specifically for the PPU. Key components of the toolchain and programming model include:

• C/C++ and OpenCL Compilers: The MetaWare Development Toolkit provides C and C++ compilers that have been extended for the PPU’s architecture, including support for auto-vectorization and intrinsic functions to manually use the vector operations. It also supports OpenCL C kernel programming, which allows developers to write compute kernels (similar to GPU programming) that can be offloaded to the PPU. These compilers are based on LLVM technology and are tuned for the ARC EV71 core, ensuring that the generated code utilizes the PPU’s vector units and CNN accelerator effectively.
• Simulation and Debugging Tools: The toolkit includes an instruction set simulator (Synopsys nSIM) for the PPU, enabling developers to simulate and profile PPU code on a PC before running on real hardware. For debugging on hardware, support is available in IDEs and external debuggers to step through PPU code. As mentioned, professional debuggers like TRACE32 support breakpoints and tracing in the PPU code concurrently with the TriCore code. This allows for debugging of heterogeneous software where, for example, a TriCore task triggers a PPU routine and one needs to follow the execution in both domains.
• DSP and Math Libraries: A collection of optimized libraries is provided for common DSP, signal processing, and linear algebra operations on the PPU. These libraries take advantage of the PPU’s vector instructions to deliver high performance for functions like FFTs, filters, matrix operations, etc., without the developer having to code these routines from scratch. By using these libraries, developers can achieve near-optimal performance on the PPU while writing mostly high-level code.
• Neural Network Development Kit: For AI applications, the MetaWare Neural Network SDK allows importing neural network models (trained in frameworks or defined in MATLAB) and compiling them into efficient PPU code. This SDK includes a neural network compiler that can optimize layers of a network to either run on the vector DSP or utilize the CNN MAC accelerator as appropriate. It essentially automates the deployment of machine learning models onto the PPU, performing tasks such as quantization, layer fusion, and scheduling to meet real-time constraints.
• AUTOSAR Integration (CDD and Drivers): Since automotive software often follows the AUTOSAR standard, Infineon provides a Complex Device Driver and low-level driver that abstract the PPU to the AUTOSAR environment. Application software can call these drivers to send tasks to the PPU, check status, or handle interruptions, all in a way that is compatible with AUTOSAR OS scheduling and safety monitoring. This is critical for ease of integration in automotive ECUs, where the PPU can be used by higher-level software components without needing to manage it at the hardware register level.
• Model-Based Design Support: Recognizing that many automotive engineers use model-based design, the toolchain supports MATLAB/Simulink workflows. Tools can automatically generate PPU-optimized code from Simulink models (using MathWorks’ support for the PPU in code generation). This means control algorithms or signal processing chains designed in Simulink can be partitioned such that parts of the model run on the TriCore and parts run on the PPU, with code generated and scheduled accordingly. This significantly speeds up development of complex algorithms by enabling simulation and auto-coding for the heterogeneous architecture.
• Real-Time Operating Systems and Hypervisor: The TC4x family supports running a hypervisor or multicore RTOS that can handle the TriCore cores and PPU together for complex software environments. HighTec’s PXROS-HR, for example, is an RTOS that supports the TC4x and can manage tasks across multiple cores with safe inter-process communication. While the PPU might not run a full OS (it typically executes dispatched tasks on bare-metal or a simple scheduler), the overall system software can orchestrate PPU usage. Developers must ensure that the time the PPU takes to complete tasks is accounted for in the real-time schedule; tools and RTOS services are available to help monitor and predict these execution times.

Overall, the development model for the PPU encourages treating it as a specialized accelerator: developers identify the parts of an application that are computational bottlenecks or can benefit from parallelization, and then offload those to the PPU using the provided toolchain (whether via explicit code, library calls, or model-based auto-generated code). The rest of the application runs on the familiar TriCore environment. This division of labor can be achieved incrementally, which is useful for legacy software migration – one can start with a fully TriCore-based application and then move certain algorithms to the PPU for performance gains, without rewriting the entire codebase.