Infineon AURIX TC3xx

Infineon AURIX™ TC3xx second-generation microcontroller (TC399 BGA package). The AURIX TC3xx family integrates multiple TriCore CPUs and on-chip safety/security modules for automotive applications.

The Infineon AURIX TC3xx (Automotive Realtime Integrated neXt-generation architecture) is a family of 32-bit automotive microcontrollers introduced as the second generation of Infineon’s AURIX platform. Launched in 2016 as a successor to the earlier AURIX TC2xx series, the TC3xx devices emphasize high performance, functional safety, and embedded security for advanced automotive and industrial applications. AURIX TC3xx microcontrollers feature a hexa-core TriCore processor architecture with enhanced safety measures, making them well-suited for demanding tasks such as autonomous driving domain controllers, powertrain control, and sensor data fusion in advanced driver-assistance systems (ADAS). The combination of multiple CPU cores, extensive on-chip memory, and a rich peripheral set allows TC3xx chips to deliver real-time responsiveness and reliability in safety-critical environments while meeting stringent automotive standards (such as ISO 26262 for functional safety).

Applications

AURIX TC3xx microcontrollers are used in a variety of safety-critical and high-performance applications across the automotive and industrial sectors. Key application domains include:

• Automotive Systems: The TC3xx family was primarily designed for automotive use and finds broad application in vehicles’ electronic control units (ECUs). Notably, it is used in powertrain and drivetrain control (engine management, transmission control, hybrid/electric vehicle inverter control, battery management) where its real-time processing and resilience support precise actuator control. It is also deployed in chassis and safety systems such as anti-lock braking systems (ABS), electronic stability control, airbag controllers, and electric power steering, leveraging its redundancy and fast response for fail-safe operation. With the growth of ADAS and autonomous driving, AURIX TC3xx devices serve as domain controllers for ADAS sensor fusion, handling data from radar, LiDAR, camera, and ultrasonic sensors and performing environment modeling and decision-making algorithms. Their combination of multiple cores and a built-in radar signal processing sub-system makes them an attractive choice for tasks like front radar processing, sensor fusion hubs, and autonomous driving domain controllers that must meet ASIL-D safety levels.
• Industrial Automation and Robotics: Infineon has also positioned the AURIX family for use in industrial applications that demand high reliability. The TC3xx MCUs, with their hardware self-test mechanisms and safety documentation, can be found in industrial motor drives, robotics controllers, and PLCs (programmable logic controllers), where they help achieve functional safety certifications up to SIL-3 (according to IEC 61508). The powerful TriCore cores and rich peripheral set enable complex motor control algorithms (e.g., field-oriented control for servo motors) and real-time sensor processing in factory automation. Additionally, the support for automotive-grade networking (CAN/CAN-FD, Ethernet) and timing peripherals makes them suitable for synchronous control in robotics and machinery. Infineon’s provision of AUTOSAR-compatible software for AURIX has even facilitated its use in non-automotive settings such as medical devices and elevator controllers, where proven safety and security are required.
• Aerospace and Defense: The high fault-tolerance and deterministic performance of the AURIX TC3xx architecture also attract interest for aerospace and other mission-critical uses. In avionics systems or autonomous drones, for instance, the lockstep core configuration and robust error checking of AURIX can provide an added layer of reliability for flight control computers or navigation systems. While primarily an automotive chip, its ability to operate in harsh conditions (−40°C to 150°C range) and to detect internal failures in real-time makes it viable for certain aerospace electronic systems. Some defense and aerospace projects leverage COTS (commercial off-the-shelf) automotive components like AURIX for applications such as unmanned vehicle control and high-reliability communication links, given its safety pedigree. (In these domains, additional analysis and possibly radiation testing would be performed if the devices are used in high-altitude or space environments.)

Architecture Overview

TC3xx Architecture Overview

Processor Cores and Architecture

The AURIX TC3xx family implements Infineon’s TriCore™ architecture, which uniquely combines aspects of RISC microcontrollers, DSP (digital signal processor) capabilities, and conventional microprocessor features into a single core design. Each TC3xx device can include up to six independent TriCore 32-bit CPU cores (TriCore version 1.6.2), all capable of running at up to 300 MHz clock frequency. Four of these cores can operate in dual-core lockstep pairs (with one core acting as a redundant checker for its partner) to provide fault detection for safety-critical functions. The TriCore cores use a superscalar Harvard architecture with 32-bit instruction words (and support for mixed 16/32-bit instruction encoding for code density). Each core includes a dedicated Floating Point Unit (FPU) for single-precision arithmetic and supports DSP-oriented instructions (e.g. single-cycle 16×16 MAC operations, SIMD for 16-bit/8-bit data) to accelerate signal processing tasks. For fast real-time performance, the architecture offers low interrupt latency (with automatic context save on-chip) and features like zero-overhead loops and a programmable peripheral timer unit for scheduling tasks. In total, a high-end TC3xx (such as the TC39x) provides six 300 MHz cores plus four checker cores, yielding a theoretical processing throughput of up to ~2400 DMIPS (Dhrystone MIPS) when all cores are utilized. This represents roughly a threefold increase in computational power over the previous AURIX generation (which achieved ~740 DMIPS with three cores).

Memory Subsystem and Cache

AURIX TC3xx microcontrollers integrate a large on-chip memory system to meet real-time and safety requirements. Program flash memory sizes range up to 16 MB on the largest models, with over 6 MB of on-chip SRAM available for data and scratchpad usage. Each TriCore CPU has its own tightly-coupled local memories as well as caches: for example, each core includes a 32 KB instruction cache and a 16 KB data cache. In addition, every core has separate local RAM blocks (Harvard architecture) for instructions and data (often termed PSPR and DSPR – Program Scratch-Pad RAM and Data Scratch-Pad RAM) that allow deterministic access for time-critical routines. Shared global memory is provided via a Local Memory Unit (LMU) which can be up to several hundred kilobytes (for instance, 768 KB in the TC39x) accessible by all cores. The memory system is connected by a high-bandwidth internal bus fabric (the SRI crossbar and peripheral buses) that arbitrates access between cores, DMA engines, and peripherals. This architecture ensures that each core can quickly fetch instructions and data either from its local cache/RAM or the central memory, enabling efficient parallel processing. Memory protection hardware is also built-in to isolate tasks of different criticality, an important feature for safety and security.

Peripherals and Interfaces

One of the strengths of the AURIX TC3xx architecture is its extensive set of on-chip peripherals and interface controllers, designed to handle the complex networking and I/O needs of modern vehicles and industrial systems. Key peripheral features and interfaces include:

• Networking Interfaces: Multiple CAN FD controllers (supporting up to 12 CAN-FD channels in high-end variants) for in-vehicle networking, with legacy CAN and LIN interfaces (up to 24 LIN channels) for lower-speed device communication. Many TC3xx devices also integrate up to two FlexRay controllers for time-triggered automotive networks (maintaining compatibility with earlier automotive communication standards). For high-bandwidth data, a Gigabit Ethernet MAC is included, enabling uses like automotive Ethernet (e.g., audio-video bridging and IP-based connectivity).
• Analog and Timers: A suite of analog peripherals including multiple ADC units for sensor interfacing and motor control, and DACs in some models. Sophisticated timer units are on-chip, notably the Generic Timer Module (GTM) and Capture/Compare Units (CCU6), which can generate complex PWM waveforms and handle events for engine control, power inverters, or robotics with minimal CPU intervention. These timers enable precise control of actuators (e.g. fuel injection timing, electric motor commutation) in real time.
• Serial Interfaces: SPI, I²C, UART/LIN and other serial interfaces for connecting to external sensors, actuator controllers, and memory. The controllers often support multiple instances (several SPI channels, etc.) to accommodate numerous devices. AURIX TC3xx also provides an external bus interface (EBU) for parallel memory or FPGA connectivity, and an SD/MMC interface (eMMC) to connect external flash memory for data logging or over-the-air update storage.
• Dedicated Processing Units: Some AURIX TC3xx models include special accelerators, such as a hardware Fast Fourier Transform unit (HW-FFT) and up to two Signal Processing Units (SPUs) optimized for radar signal processing. These enable the microcontroller to handle radar front-end data or other intensive DSP tasks (like Fourier transforms for radar or audio signals) on-chip, which is crucial for advanced driver assistance sensors. There is also a Security Module (covered in a later section) and a Safety Management Unit that supervise system integrity.
• Other On-chip Modules: Watchdog timers, error-correction coders for memories (ECC on flash and RAM for reliability), a programmable interrupt system, multiple DMA channels (up to 128 DMA channels) for efficient data movement, and debug interfaces (JTAG and a 2/3-pin DAP) for development. The on-chip debug system supports tracing of program execution (via a built-in Emulation Memory, MCDS) to aid in complex multicore software development.

Overall, the AURIX TC3xx provides a highly integrated SoC-like platform, allowing a single chip to manage tasks ranging from powertrain control and chassis control to infotainment gateways. This high level of integration reduces the need for separate companion chips and helps to lower system complexity and cost.

Performance and Benchmarking

Fabricated in a 40 nm embedded flash process, AURIX TC3xx processors achieve significant performance gains over prior generations while maintaining automotive-grade power efficiency. With six 32-bit cores at 300 MHz (four of them paired in lockstep), a flagship TC3xx device (e.g., TC39x) can deliver up to approximately 2,400 DMIPS of aggregate computing throughput. In terms of per-core performance, the TriCore architecture yields around 1.3–2.0 DMIPS/MHz depending on the instruction mix, meaning each 300 MHz core can approach ~400–600 DMIPS in optimized scenarios. This is on par with or exceeding many contemporary 32-bit automotive MCUs. The integrated DSP extensions and optional accelerators (like the FFT unit) also enable high-speed signal processing, with Infineon citing up to ~1.8 GFLOPS of DSP throughput for certain operations.

Real-world performance improvements of the TC3xx over its predecessor are notable: for example, compared to the first-generation AURIX (which offered up to 740 DMIPS), the TC3xx’s expanded core count and clock speed provide roughly three times the computational power on the same type of workload. This extra headroom allows more functions (such as running multiple control algorithms or sensor fusion tasks in parallel) to be consolidated onto one microcontroller without compromising real-time deadlines. Despite the increase in speed and core count, the TC3xx family was designed with power and thermal constraints in mind, achieving these gains within similar power consumption envelopes as the previous generation by leveraging the smaller 40 nm process and power-saving features like clock gating. The deterministic real-time performance (with features like lockstep and tightly-coupled memory) makes the AURIX TC3xx suitable for the most demanding automotive applications, where consistent low latency and high throughput are required simultaneously.

On-Chip System Connectivity and Bridges

The TC3xx has two SRI Domains (SRI0 and SRI1). CPU0 to CPU3 are connected to SRI0, CPU4/5 are connected to SRI1.

The AURIX™ TC3xx Platform has three independent on-chip connectivity resources:

• System Resource Interconnect Fabric (SRI Fabric) connects the TriCore CPUs, the DMA module, and other high bandwidth requestors to high bandwidth memories and other resources for instruction fetches and data accesses. A key component of the fabric is the SRI crossbar, which connects all the agents in one SRI domain. The SRI crossbar carries the transactions between the SRI Masters and SRI Slaves of the domain. The SRI crossbar supports parallel transactions between different SRI Master and SRI Slave agents. In addition to the parallelism of concurrent requests, it also supports pipelined requests from an SRI Master to a SRI Slave.
• System Peripheral Bus (SPB) connects the TriCore CPUs, the DMA module, and other SPB masters to the medium and low bandwidth peripherals. SPB masters do not directly connect to the SRI Fabric, and will access SRI attached resources via a SFI_F2S Bridge.
• Back Bone Bus (BBB) connects the TriCore CPUs, the DMA module, and SPB masters with ADAS resources. SRI Masters do not directly connect to the BBB, but access BBB attached resources via a SFI_S2F Bridge. SPB masters also do not directly connect to the BBB, but access BBB attached resources via bridging over the SRI Fabric.

CPU Resource Access Times

These tables describe the CPU access times to various resources in CPU clock cycles for the AURIX™ TC3xx Platform. In the case of load or fetch accesses, the access times are the minimum number of CPU stall cycles to complete the access. If there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

For write access, the access times are the maximum for a sequence of such access (non-conflicting). In many cases for a singleton access, or a short sequence, write buffering reduces the stall effect seen by a CPU, sometimes to 0. However, as with loads and fetches, if there is a conflict for the resource accessed, there may be additional stall cycles till the conflicting access completes.

Access latency for global resources

CPU Access Type	CPU stall cycles	Notes
Data read from System Peripheral Bus (SPB)	${\frac {f_{\text{CPU}}}{f_{\text{SPB}}}}\cdot (4+{\text{Module Wait State}})$	The final number of stall cycles will depend on the real number of WS generated by the target resource.
Data write to System Peripheral Bus (SPB)	${\frac {f_{\text{CPU}}}{f_{\text{SPB}}}}\cdot (4+{\text{Module Wait State}})$
Data read from Back Bone Bus (BBB) (TC39x, TC37xED)	$9+{\frac {f_{\text{CPU}}}{f_{\text{BBB}}}}\cdot (5+{\text{Module Wait State}})$	When SFI_S2F is connected to XBar2 (TC39x and TC37xED) there is an additional latency due to access going through an S2S.
Data write to Back Bone Bus (BBB) (TC39x, TC37xED)	$5+{\frac {f_{\text{CPU}}}{f_{\text{BBB}}}}\cdot (4+{\text{Module Wait State}})$
Data read from Back Bone Bus (BBB) (TC35x, TC33xED)	$6+{\frac {f_{\text{CPU}}}{f_{\text{BBB}}}}\cdot (5+{\text{Module Wait State}})$
Data write to Back Bone Bus (BBB) (TC35x, TC33xED)	$3+{\frac {f_{\text{CPU}}}{f_{\text{BBB}}}}\cdot (4+{\text{Module Wait State}})$

• Module Wait State: The number of wait states for read and for write accesses is >= 1 and depends on the accessed module and its configuration.

CPU Accesses: Stall cycles for local and SRI resources

CPU Access Type	Local CPU	Local SRI	Remote SRI Domain
Data read from DSPR	0	7	10
Data write to DSPR	0	5, 3 (with Pipelining)	5, 4 (with Pipelining)
Instruction fetch from DSPR	See local SRI column	7	10
Data read from DLMU	0	7	10
Data write to DLMU	2	5, 3 (with Pipelining)	5, 4
Instruction fetch from DLMU	See local SRI column	7	10
Data read from PSPR	See local SRI column	7	10
Data write to PSPR	See local SRI column	5, 3 (with Pipelining)	5, 4 (with Pipelining)
Instruction fetch from PSPR	0	7	10
Data read from PFlash	5 + PWS	10 + PWS	13 + PWS
Instruction fetch from PFlash (buffer miss)	2 + PWS	9 + PWS	12 + PWS
Instruction fetch from PFlash (buffer hit)	3	6	9
Data read from LMU	n.a.	7	10
Data write to LMU	n.a.	5, 3 (with Pipelining)	5, 4 (with Pipelining)
Instruction fetch from LMU	n.a.	7	10
Data read from DFlash	n.a.	5 + 3*(3 + DCWS)	8 + 3*(3 + DCWS)
Data read access from EMEM (TC39x, TC37xED)	n.a.	n.a.	14, 15 (fBBB < fSRI)
Data write access to EMEM (TC39x, TC37xED)	n.a.	n.a.	9
Data read access from EMEM (TC35x, TC33xED)	n.a.	11, 12 (fBBB < fSRI)	n.a.
Data write access to EMEM (TC35x, TC33xED)	n.a.	9	n.a.
Data read access from DAM	n.a.	10	13
Data write access to DAM	n.a.	7	7

• Remote SRI Domain: Only applies to products with SRI extenders. Additional latency due to access going through an S2S
• PWS: Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
• PWS: Configured PFlash Wait States (Includes cycles for PFlash access cycles only). ECC correction latency is only incurred when the incoming data requires ECC correction.
• DCWS: Configured DFlash Corrected Wait States (Includes cycles for DFlash access cycles and ECC correction latency)

CPU Subsystem

Processor Core, Local Memory and Connectivity

The Infineon AURIX TC3xx features up to 6 processor cores (CPU0 ... CPU5) implementing the TC1.6.2 instruction set architecture. The following section focuses on the microarchitectural details of the CPU subsystem. For more information about the ISA, please take a look at the TriCore Instruction Set Architecture.

The processor core connects to the following memories and bus interfaces (where implemented):

• Program Scratch-Pad SRAM (PSPR)
• Data Scratch-Pad SRAM (DSPR)
• Program Cache (PCache)
• Data Cache (DCache)
• Local Memory Unit (DLMU)
• Local Pflash bank (LPB)
• SRI slave interface (x2)
• SRI master Interface
• SPB master interface

TC1.6.2P Implementation Features

• Most instructions executed in 1 cycle
• Branch instructions in 1, 2 or 3 cycles (using dynamic branch prediction)
• Wide memory interface for fast context switch
• Automatic context save-on-entry and restore-on-exit for: subroutine, interrupt, trap
• Six memory protection register sets
• Dual instruction issuing (in parallel into Integer Pipeline and Load/Store Pipeline)
• Third pipeline for loop instruction only (zero overhead loop)
• Single precision Floating Point Unit (IEEE-754 Compatible)
• Dedicated Integer divide unit
• 18 data memory protection ranges, 10 code memory protection ranges arranged in 6 sets

Superscalar Architecture

The processor core within the AURIX TC3xx family, specifically the TC1.6.2P implementation, employs a superscalar architecture characterized by three parallel pipelines: the Integer Pipeline, the Load/Store Pipeline, and the Loop Pipeline. Superscalar execution is a form of instruction-level parallelism that enables the processor to issue and execute multiple instructions during a single clock cycle. The TriCore TC3xx core's superscalar architecture allows it to issue and execute multiple instructions in parallel. Specifically, it can issue up to two instructions simultaneously to the Integer and Load/Store pipelines. However, there are certain constraints on this dual issuing capability. For example, back-to-back data arithmetic instructions can only be issued in separate cycles, and a load/store instruction can be issued either on its own or paired with a data arithmetic instruction, provided the load/store instruction is the second in the pair. Under ideal conditions, with careful instruction scheduling, this dual-issue capability can lead to a throughput of close to 0.5 clock cycles per instruction, effectively executing two instructions per cycle.

Pipeline Stages

The execution of instructions within the TriCore TC3xx core is managed through a pipeline consisting of several stages. In one document it is mentioned that the pipeline consists of 6 stages , but the exact stages remain unclear. From the architecture the following stages can be inferred:

• Fetch Stage: The initial stage in the pipeline is the Fetch stage, where instructions are retrieved from memory. This task is handled by the Instruction Fetch Unit (IFU), which is responsible for fetching instructions from the memory system. To improve efficiency, the IFU employs a pre-fetching mechanism, anticipating the instructions that will be needed and bringing them into the processor before they are actually required. Instructions are fetched through a 64-bit wide Program Memory Interface (PMI), allowing for the retrieval of a significant amount of instruction data in each cycle. The fetched instructions are then placed into an issue FIFO, a buffer capable of holding up to six instructions. This buffer plays a crucial role in managing the flow of instructions to the subsequent execution pipelines. The 64-bit fetch width and the instruction buffer are indicative of a design that aims to ensure a continuous supply of instructions to the pipelines, preventing them from being starved of work. A wider fetch path allows for more instruction bits to be obtained from memory in each clock cycle, while the buffer helps to mitigate temporary delays in instruction fetching.
• Execution Unit: The Execution Unit contains the Integer Pipeline, the Load/Store Pipeline and the Loop Pipeline. All three pipelines operate in parallel and are capable of executing instructions simultaneously. Each pipline has its own decode stage and two execute stages. Furthermore, the TC3xx features a Floating Point Unit (FPU). It is not clear whether the FPU is part of the execution unit or a separate unit. It is assumed that the FPU also has its own decode stage and an unknown number of execute stages
  • Decode Stage: Following the Fetch stage, the instruction are issued to one of the pipelines. In the decode stage of each pipeline, the instruction is examined and translated to determine the specific operation it represents and to identify the operands it will operate on. It is assumed that operands are read from the register file during the decode stage.
  • Execute Stage: The Execute stage is where the actual operation specified by the instruction is carried out. Pipeline hazards (stalls) are minimised by the use of forwarding paths between pipeline stages allowing the results of one instruction to be used by a following instruction as soon as the result becomes available.
  • Writeback Stage: The final stage in the pipeline is the Writeback stage. In this stage, the results produced by the executed instruction are written back to the processor's register file, making them available for subsequent instructions. It is unclear whether the writeback stage is part of the (two) execution stages or a separate stage.

Execution Pipelines

The TriCore TC3xx core leverages four parallel pipelines to enhance its performance. Each pipeline is designed to handle a specific class of instructions:

• Integer Pipeline: This pipeline is responsible for executing integer arithmetic and logical instructions, including data-conditional jump instructions, bit manipulation operations, as well as division and multiply-accumulate (MAC) instructions.
• Load/Store Pipeline: The primary function of this pipeline is to manage memory access operations, including loading data from memory and storing data to memory. It also handles address arithmetic, unconditional jump instructions, procedure call instructions, context-switching operations, and control flow related to context save areas (CSAs).
• Loop Pipeline: This is a specialized pipeline designed to facilitate zero-overhead loops, a technique that significantly improves the performance of iterative code sections. Its design aims to eliminate or minimize the overhead typically associated with loop control, such as incrementing counters and checking loop conditions. Some documentation suggests that the loop pipeline comes along with a "Loop Cache". This dedicated cache would likely be used to store instructions belonging to the loop, enabling very fast access and execution for repeated iterations.
• Floating Point Unit (FPU): The FPU is responsible for executing floating-point arithmetic operations

Store Buffers

The TriCore TC3xx core include Store Buffers to decouple memory write operations from CPU instruction execution. All stores from the Load/Store Pipeline are placed in the store buffer prior to being written to local memory or transferred via the bus system. Write data is taken from the store buffers and written to memory when the target memory or bus interface becomes available. In normal operation the CPU will prioritise memory load operations over store operations in order to improve performance unless the store buffer is full or the order of load and store operations must be preserved (e.g. peripheral space access). The store buffer can hold the data for up to 6 stores operations. To improve performance the store buffer will merge consecutive byte, half-word, and word writes of the same location to reduce the number of memory accesses required.

Functional Safety and Security Features

Hardware Security Module and Encryption

One of the defining features of the AURIX TC3xx family is its robust hardware-based security subsystem, implemented to protect against cyber threats and unauthorized manipulation of vehicle systems. Each TC3xx MCU includes a dedicated Hardware Security Module (HSM), which is essentially an on-chip co-processor with its own CPU and cryptographic engine designed to handle secure operations. In the second-generation AURIX (TC3xx), the HSM was upgraded with support for asymmetric cryptography (e.g., RSA, ECC algorithms) in hardware, providing significantly faster public-key encryption and authentication capabilities than pure software implementations. This HSM supports EVITA Full (the highest level of the EU’s EVITA automotive security requirements), meaning it can perform secure boot, message authentication, and encryption at a level suitable for protecting critical in-vehicle communications. For example, the HSM can encrypt and authenticate CAN/Ethernet messages to prevent spoofing or tampering on the vehicle network, and it can manage cryptographic keys securely isolated from the main application cores.

The security module enables features like secure boot, where the AURIX will only execute firmware that is digitally signed by the vehicle manufacturer, thereby preventing unauthorized or malicious code. It also facilitates over-the-air (OTA) updates in a secure manner: the TC3xx HSM can verify and decrypt update packages received via telematics, allowing firmware upgrades while protecting against attackers attempting to hijack the software. In addition, the HSM includes a true random number generator and supports protocols for immobilizer and theft protection systems. Infineon’s implementation essentially treats the HSM as an “embedded smart card” inside the microcontroller. This approach, building on Infineon’s expertise in chip card security, helps to safeguard sensitive assets like cryptographic keys and to perform secure operations (encryption, decryption, authentication) in hardware, making attacks significantly more difficult. The strong cybersecurity provisions of the AURIX TC3xx have made it a preferred choice for vehicle gateway ECUs and central body controllers, which are points of entry for connected car communications and thus high-value targets for hackers. By incorporating the HSM, automotive OEMs can implement advanced security features such as encrypted onboard communication (to thwart bus tampering) and secure diagnostics, ensuring the vehicle’s electronic data is protected against cyber threats even as cars become more connected.

Functional Safety and Fault Tolerance

Beyond cybersecurity, the AURIX TC3xx architecture is built with extensive functional safety features to meet the highest safety integrity levels in automotive systems. The multi-core design supports lockstep operation, where redundant checker cores run in parallel with main cores and continuously compare results cycle-by-cycle. In TC3xx devices, up to four of the six TriCore CPUs have such lockstep partner cores, allowing the microcontroller to detect any single-point CPU failure instantly (if a discrepancy arises between the core and its checker, a fault is signaled). A Safety Management Unit (SMU) is integrated on-chip to monitor various fault conditions throughout the device – it aggregates error signals from the lockstep cores, memory ECC monitors, clock/watchdog monitors, and peripheral self-tests, and can initiate safe-state actions (like resetting the chip or signaling an error pin to an external supervisor) if a critical fault is detected. The AURIX safety concept also includes a distributed Memory Protection Unit (MPU) arrangement, with multiple memory protection contexts that prevent errant or malicious code from writing to wrong memory areas. This helps contain faults and eases the integration of software with mixed criticality (Infineon allows partitioning software components of different ASIL levels on the same MCU while keeping them isolated).

Crucially, the TC3xx family was developed according to ISO 26262 processes and can achieve ASIL-D (Automotive Safety Integrity Level D), the highest grade for automotive functional safety. Compared to a traditional dual-core lockstep approach, the AURIX’s multi-core safety architecture allowed Infineon to reduce certain safety development overheads (earlier Infineon data suggested up to 30% reduction in safety software workload) by providing built-in safety mechanisms and diagnostics. Infineon supplies a comprehensive safety manual and diagnostic libraries for the AURIX, helping engineers utilize features like CPU self-tests, RAM tests, and CRC checks to comply with safety standards. In addition to automotive standards, the AURIX TC3xx has also been qualified for industrial safety: in 2023, Infineon announced support for IEC 61508 metrics, enabling designs with AURIX to reach SIL-2 and SIL-3 safety integrity levels for industrial applications. This cross-industry safety compliance is facilitated by the MCU’s redundant design and detailed failure mode documentation (FMEDA) provided by Infineon. In summary, the AURIX TC3xx integrates both proactive safety (fault prevention via lockstep, monitoring and protection) and reactive safety (fault detection and safe shutdown), making it a dependable component for systems that cannot afford unintended behavior, whether in cars, factories, or aerospace.

Platform Devices

The following table shows a feature overview of the AURIX™ TC3xx Platform family focusing on memory and number of cores.

	Feature	TC33x	TC33xEXT	TC35x	TC36x	TC37x	TC37xEXT	TC38x	TC39x
CPUs	Cores / Checker Cores	1 / 1	2 / 1	3 / 2	2 / 2	3 / 2	3 / 3	4 / 2	6 / 4
	Max. Freq.	300 MHz
Cache per CPU	Program [KB]	32
	Data [KB]	16
SRAM per CPU	PSPR [KB]	8	32 (CPU0) 64 (other)	64	32	64	64	64	64
	DSPR [KB]	192	192 (CPU0) 64 (other)	240 (CPU0&1) 64 (other)	192	240 (CPU0&1) 64 (other)	240 (CPU0&1) 64 (other)	240 (CPU0&1) 64 (other)	240 (CPU0&1) 64 (other)
	DLMU [KB]	8	8 (CPU0) 64 (other)	64	64	64	64	64	64
SRAM global	LMU [KB]	-	-	512	-	-	-	128	768
	DAM [KB]	-	-	32	-	64	64	128	128
Extension Memory (EMEM)	TCM [MB]	-	1	2	-	-	2	-	2
	XCM [MB]	-	-	-	-	-	1	-	2
	XTM [KB]	-	16	16	-	-	16	-	16
Program Flash	Size [MB]	2	4	4	4	6	10	10	16
	Banks [MB]	1 x 2	2 x 2	2 x 2	2 x 2	2 x 3	3 x 3, 1 x 1	3 x 3, 1 x 1	5 x 3, 1 x 1
Data Flash	DF0 Size (single-ended) [KB]	128	128	128	128	256	512	512	1024
	DF1 Size (single-ended) [KB]	128	128	128	128	128	128	128	128
DMA	Channels	64	64	64	64	128	128	128	128
	Move Engines	2	2	2	2	2	2	2	2
	Resource Partitions	4	4	4	4	4	4	4	4

Compilers

The AURIX TC3xx family is a series of high-performance microcontrollers widely used in automotive and industrial applications. Compilers for the AURIX TC3xx are crucial for developers aiming to optimize performance, reliability, and safety in their applications. One significant aspect of the compiler landscape for AURIX TC3xx is the limited direct support from mainline open-source compilers such as GCC or LLVM/Clang. The primary reason for this is the stringent requirements for functional safety in automotive and industrial applications, which demand specialized features and compliance with safety standards that are often not met by general-purpose open-source compilers.

Commercial Compilers

1. Tasking: Tasking compilers are renowned for their robust support for automotive applications, offering advanced debugging capabilities and optimization techniques tailored for the AURIX architecture. They provide extensive code optimization, comprehensive debugging tools, and strong support for safety standards such as ISO 26262, making them ideal for developing high-performance, reliable, and safe applications.
2. HighTec: The HighTec compiler is a popular choice, known for its Eclipse-based development environment and strong multicore support. HighTec provides both GCC and LLVM-based ports of open-source compilers tailored specifically for the AURIX TC3xx family. These compilers offer efficient parallel execution, advanced code analysis, and an integrated development environment, ensuring robust performance and compliance with safety standards.
3. Green Hills Software: Green Hills Software provides a highly optimized toolchain aimed at safety-critical applications, focusing on high performance and strict compliance with automotive standards. Their compiler offers superior optimization, extensive safety features, and a proprietary IDE with specialized tools for automotive development, ensuring developers can meet the stringent demands of functional safety.

GCC for AURIX

While mainline GCC does not directly support the AURIX TC3xx family, there is an unofficial GCC version available for AURIX. Due to the GNU General Public License (GPL), the source code from HighTec was retrieved and, along with binary versions, published on GitHub:

• GCC 4.9.4/Binutils 2.20/Newlib 1.18 for Tricore Aurix [Source] [Prebuild Mingw Binaries] [Prebuild Linux Binaries]
• GCC 9.4.0/Binutils 2.20/Newlib 1.18 for Tricore Aurix [Source] [Prebuild Mingw Binaries] [Prebuild Linux Binaries]
• GDB 10.0.50 for Tricore Aurix [Source]

emmtrix Tools for AURIX TC3xx

emmtrix Technologies is an Infineon Associated Partner with over 10 years of experience working with the Infineon AURIX™ microcontroller family and has been actively collaborating with Infineon for the past five years.

emmtrix offers the following tool for the Infineon AURIX TC3xx architecture:

emmtrix Performance Estimator

emmtrix Performance Estimator (ePE) provides static timing analysis of C code. Compared to simulation or measurement on hardware, static performance analysis can be applied significantly earlier in the development process and will deliver results on average 6 months earlier compared to a typical automotive HIL setup. The analysis only takes a few minutes at most and runs on the developer’s PC independently of any target hardware. Function developers can analyze their runnables or SWCs without the need of a fully integrated program. emmtrix Performance Estimator is fully compatible with Infineon's AURIX™ TC2xx / TC3xx/ TC4x microcontroller family, ensuring precise and reliable performance analysis for embedded systems.

A unique feature is the combination with TargetLink or Embedded Coder generated code. Without any measurement overhead, our static performance estimation can analyze even the smallest code snippets. This allows us to map the timing analysis to Simulink blocks, giving function developers insight into the timing behavior of their models.

ePE offers three accuracy levels:

• analysis of C code
• generically compiler-optimized code
• assembly code from the target compiler.

Method 1 yields results with minimum effort while method 3 takes the timing of the processor pipeline into account. All methods offer excellent reliability when tracking the tendency of changes in software runtimes e.g. when used in a continuous integration environment.

See Also

• Infineon AURIX TC4x
• Infineon AURIX TC2xx
• TriCore Instruction Set Architecture

External Links

• https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricore-aurix-tc3xx/
• AURIX TC3xx user manuals
  • AURIX™ TC3xx User Manual Part-1
  • AURIX™ TC3xx User Manual Part-2
  • AURIX™ TC3xx Architecture vol 1
  • AURIX™ TC3xx Architecture vol 2