TriCore Instruction Set Architecture

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TriCore is a unified, 32-bit microcontroller-DSP, single-core architecture optimized for real-time embedded systems The ISA supports a uniform, 32-bit address space, with optional virtual addressing and memory-mapped I/O The architecture allows for a wide range of implementations, ranging from scalar through to superscalar, and is capable of interacting with different system architectures, including multiprocessing This flexibility at the implementation and system levels allows for different trade-offs between performance and cost at any point in time

The architecture supports both 16-bit and 32-bit instruction formats All instructions have a 32-bit format The 16-bit instructions are a subset of the 32-bit instructions, chosen because of their frequency of use These instructions significantly reduce code space, lowering memory requirements, system and power consumption

Real-time responsiveness is largely determined by interrupt latency and context-switch time The high-performance architecture minimizes interrupt latency by avoiding long multi-cycle instructions and by providing a flexible hardware-supported interrupt scheme The architecture also supports fast-context switching

Versions

ISA Processors User Manual Date New Instructions
TC13 2002-05
TC131 TriCore™ Family AUDO MAX 2007-11
  • CACHEIW, CACHEIWI
  • FTOIZ, FTOQ31Z, FTOUZ (FPU Conversion Instructions)
TC16 Infineon AURIX TC2xx 2013-07
  • DISABLE, RESTORE, CACHEII (Interrupt and Data Cache manipulation)
  • DIV, DIVU (Fast Integer Divide)
  • FCALL,FCALLA,FCALLI, FRET (fast call and return with minimal saving of state)
  • LDBU, LDB, LDHU, LDH, STB, STH, STA (Long offset addressing mode introduced for byte, half word and address accesses)
  • JEQ, JNE (Extended range of 16 bit jumps)
  • CMPSWAPW, SWAPMSKW (New Synchronisation Instructions)
  • CRC32 (New CRC instruction)
  • WAIT (New wait for interrupt instruction)
TC162 Infineon AURIX TC3xx 2017-01
  • CRC32BW, CRC32LW, CRC32B (CRC32 for big endian, little endian and byte data)
  • CRCN (arbitrary width and polynomial CRC calculation)
  • SHUFFLE (Reorder bytes within word)
  • POPCNT (count number of bits set in word)
  • FTOHP, HPTOF (Half precision floating point conversion)
  • LHA (Load high bits of address value)
TC18 Infineon AURIX TC4x N/A N/A (user manual not yet public available)

Features

The key features of the TriCore Instruction Set Architecture (ISA) are:

  • 32-bit load store architecture
  • 4 Gbyte address range (232)
  • 16-bit and 32-bit instructions for reduced code size
  • Data types:
    • Boolean, integer with saturation, bit array, signed fraction, character, double-word integers, signed integer, unsigned integer, IEEE-754 single-precision floating point
  • Data formats:
    • Bit, byte (8-bits), half-word (16-bits), word (32-bits), double-word (64-bits)
  • Byte and bit addressing
  • Little-endian byte ordering for data, memory and CPU registers
  • Multiply and Accumulate (MAC) instructions: Dual 16 × 16, 16 × 32, 32 × 32
  • Saturation integer arithmetic
  • Packed data
  • Addressing modes:
    • Absolute, circular, bit reverse, long + short, base + offset with pre- and post-update
  • Instruction types:
    • Arithmetic, address arithmetic, comparison, address comparison, logical, MAC, shift, coprocessor, bit logical, branch, bit field, load/store, packed data, system
  • General Purpose Register Set (GPRS):
    • Sixteen 32-bit data registers
    • Sixteen 32-bit address registers
    • Three 32-bit status and program counter registers (PSW, PC, PCXI)
  • Debug support (OCDS):
    • Level 1, supported in conjunction with the CPS block
    • Level 3, supported in conjunction with the MCDS block (Emulation Device only)
  • Flexible memory protection system providing multiple protection sets with multiple protection ranges per set
  • Temporal protection system allowing time bounded real time operation

Register Set

Architectural Registers

The architectural registers consist of:

  • 32 General Purpose Registers (GPRs)
    • 16 Address Registers
    • 16 Data Registers
  • Program Counter (PC)
  • Two 32-bit registers containing status flags
32-bit Architectural Registers
Address Register
A[15] Implicit Base Address
A[14]
A[13]
A[12]
A[11] Return Address
A[10] Stack Pointer (SP)
A[9] Global Address Register
A[8] Global Address Register
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1] Global Address Register
A[0] Global Address Register
Data Register
D[15] Implicit Data
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
System Register
PCXI Previous Context Information
PSW Program Status Word
PC Program Counter

Special Registers

General Special Registers
PC Program Counter Register
SYSCON System Configuration Register
CPU_ID CPU Identification Register (Read Only)
CORE_ID Core Identification Register
BIV Base Address of Interrupt Vector Table Register
BTV Base Address of Trap Vector Table Register
ISP Interrupt Stack Pointer Register
ICR ICU Interrupt Control Register
FCX Free Context List Head Pointer Register
LCX Free Context List Limit Pointer Register
COMPAT Compatibility Mode Register
Debug Registers
DBGSR Debug Status Register
EXEVT External Event Register
CREVT Core Register Event Register
SWEVT Software Event Register
TR0EVT Trigger Event 0 Register
TR0ADR Trigger Address 0 Register
⋮
TR7EVT Trigger Event 7 Register
TR7ADR Trigger Address 7 Register
TRIG_ACC Trigger Accumulator Register
DMS Debug Monitor Start Address Register
DCX Debug Context Save Address Register
TASK_ASI TASK Address Space Identifier Register
DBGTCR Debug Trap Control Register
CCTRL Counter Control Register
CCNT CPU Clock Count Register
ICNT Instruction Count Register
M1CNT Multi Count Register 1
M2CNT Multi Count Register 2
M3CNT Multi Count Register 3
Floating Point Registers
FPU_TRAP_CON Trap Control Register
FPU_TRAP_PC Trapping Instruction Program Control Register
FPU_TRAP_OPC Trapping Instruction Opcode Register
FPU_TRAP_SRC1 Trapping Instruction SRC1 Operand Register
FPU_TRAP_SRC2 Trapping Instruction SRC2 Operand Register
FPU_TRAP_SRC3 Trapping Instruction SRC3 Operand Register

Instructions Set

Pipeline

Acronym Pipeline
LS Load/Store
IP Integer Pipeline
FPU Floating Point Unit

Classes

Class Pipeline Description Example
Arithmetic LS Arithmetic operations involving addresses ADDA, ADDIHA
Arithmetic IP Arithmetic operations involving integers ADD, SUB
Cache LS Cache management operations CACHEAW, CACHEAWI
Compare IP Comparison operations EQ, GE
Control Flow LS Control flow instructions for branching J, JNEA
Control Flow IP Control flow operations for branching JEQ, JLT
Coprocessor 0 IP Special operations using coprocessor 0 CRC32B, IXMAX
Count IP Counting bits in registers CLO, CLZ
CSA Control Flow LS Context Save Areas (CSA) control flow instructions CALL, BISR
Extract IP Bit field extraction and manipulation DEXTR, INST
Floating Point FPU Floating-point instructions ADDF, SUBF
Integer Divide IP Integer division operations DIV, DVSTEP
Load LS Load data from memory LDA, LDUCX
Logical IP Bitwise logical operations AND, OR
Move LS Move data between address registers MOVA, MOVAA
Move IP Move data between data registers CMOV, MOV
Multiply IP Multiplication operations MUL, MULS
Multiply Accumulate IP Multiply and accumulate operations MADD, MSUB
Shift IP Bit shift operations SH, SHA
Store LS Store data to memory STA, STB
Sync LS Synchronization operations DSYNC, ISYNC
Trap and Interrupt LS Interrupt and trap operations DEBUG, TRAPV

Instruction List

Pipeline Class Mnemonic Longname ISA Version
LS Arithmetic ADDA Add Address
LS Arithmetic ADDIHA Add Immediate High to Address
LS Arithmetic ADDSCA Add Scaled Index to Address
LS Arithmetic ADDSCAT Add Bit-Scaled Index to Address
LS CSA Control Flow BISR Begin Interrupt Service Routine
LS Cache CACHEAI Cache Address, Invalidate
LS Cache CACHEAW Cache Address, Writeback TC131
LS Cache CACHEAWI Cache Address, Writeback and Invalidate TC131
LS Cache CACHEIW Cache Index, Writeback
LS Cache CACHEII Cache Index, Invalidate TC16
LS Cache CACHEIWI Cache Index, Writeback, Invalidate
LS CSA Control Flow CALL Call
LS CSA Control Flow CALLA Call Absolute
LS CSA Control Flow CALLI Call Indirect
LS Load CMPSWAPW Compare and Swap TC16
LS Trap and Interrupt DEBUG Debug
LS Trap and Interrupt DISABLE Disable Interrupts TC16
LS Sync DSYNC Synchronize Data
LS Trap and Interrupt ENABLE Enable Interrupts
LS Arithmetic EQA Equal to Address
LS Arithmetic EQZA Equal Zero Address
LS CSA Control Flow FCALL Fast Call TC16
LS CSA Control Flow FCALLA Fast Call Absolute TC16
LS CSA Control Flow FCALLI Fast Call Indirect TC16
LS CSA Control Flow FRET Return from Fast Call TC16
LS Arithmetic GEA Greater Than or Equal Address
LS Sync ISYNC Synchronize Instructions
LS Control Flow J Jump Unconditional
LS Control Flow JA Jump Unconditional Absolute
LS Control Flow JEQA Jump if Equal Address
LS Control Flow JI Jump Indirect
LS Control Flow JL Jump and Link
LS Control Flow JLA Jump and Link Absolute
LS Control Flow JLI Jump and Link Indirect
LS Control Flow JNEA Jump if Not Equal Address
LS Control Flow JNZA Jump if Not Equal to Zero Address
LS Control Flow JZA Jump if Zero Address
LS Load LDA Load Word to Address Register
LS Load LDB Load Byte TC16*
LS Load LDBU Load Byte Unsigned TC16*
LS Load LDD Load Double-word
LS Load LDDA Load Double-word to Address Register
LS Load LDH Load Half-word TC16*
LS Load LDHU Load Half-word Unsigned TC16*
LS Load LDQ Load Half-word Signed Fraction
LS Load LDW Load Word
LS Load LDLCX Load Lower Context
LS Store LDMST Load-Modify-Store
LS Load LDUCX Load Upper Context
LS Load LEA Load Effective Address
LS Load LHA Load High Address TC162
LS Control Flow LOOP Loop
LS Control Flow LOOPU Loop Unconditional
LS Arithmetic LTA Less Than Address
LS Move MFCR Move From Core Register
LS Move MOVA Move Value to Address Register
LS Move MOVAA Move Address from Address Register
LS Move MOVD Move Address to Data Register
LS Move MOVHA Move High to Address
LS Move MTCR Move To Core Register
LS Arithmetic NEA Not Equal Address
LS Arithmetic NEZA Not Equal Zero Address
LS Arithmetic NOP No Operation
LS Trap and Interrupt RESTORE Restore TC16
LS CSA Control Flow RET Return from Call
LS CSA Control Flow RFE Return From Exception
LS CSA Control Flow RFM Return From Monitor
LS CSA Control Flow RSLCX Restore Lower Context
LS Store STA Store Word from Address Register TC16*
LS Store STB Store Byte TC16*
LS Store STD Store Double-word
LS Store STDA Store Double-word from Address Registers
LS Store STH Store Half-word TC16*
LS Store STQ Store Half-word Signed Fraction
LS Store STT Store Bit
LS Store STW Store Word
LS Store STLCX Store Lower Context
LS Store STUCX Store Upper Context
LS Arithmetic SUBA Subtract Address
LS CSA Control Flow SVLCX Save Lower Context
LS Load SWAPW Swap with Data Register
LS Load SWAPMSKW Swap under Mask TC16
LS CSA Control Flow SYSCALL System Call
LS Trap and Interrupt TRAPSV Trap on Sticky Overflow
LS Trap and Interrupt TRAPV Trap on Overflow
LS Trap and Interrupt WAIT Wait TC16
IP Arithmetic ABS Absolute Value
IP Arithmetic ABSB Absolute Value Packed Byte
IP Arithmetic ABSH Absolute Value Packed Half-word
IP Arithmetic ABSDIF Absolute Value of Difference
IP Arithmetic ABSDIFB Absolute Value of Difference Packed Byte
IP Arithmetic ABSDIFH Absolute Value of Difference Packed Half-word
IP Arithmetic ABSDIFS Absolute Value of Difference with Saturation
IP Arithmetic ABSDIFSH Absolute Value of Difference Packed Half-word with Saturation
IP Arithmetic ABSS Absolute Value with Saturation
IP Arithmetic ABSSH Absolute Value Packed Half-word with Saturation
IP Arithmetic ADD Add
IP Arithmetic ADDB Add Packed Byte
IP Arithmetic ADDH Add Packed Half-word
IP Arithmetic ADDC Add with Carry
IP Arithmetic ADDI Add Immediate
IP Arithmetic ADDIH Add Immediate High
IP Arithmetic ADDS Add Signed with Saturation
IP Arithmetic ADDSH Add Signed Packed Half-word with Saturation
IP Arithmetic ADDSHU Add Unsigned Packed Half-word with Saturation
IP Arithmetic ADDSU Add Unsigned with Saturation
IP Arithmetic ADDX Add Extended
IP Logical AND Bitwise AND
IP Logical ANDANDT Accumulating Bit Logical AND-AND
IP Logical ANDANDNT Accumulating Bit Logical AND-AND-Not
IP Logical ANDNORT Accumulating Bit Logical AND-NOR
IP Logical ANDORT Accumulating Bit Logical AND-OR
IP Logical ANDEQ Equal Accumulating
IP Logical ANDGE Greater Than or Equal Accumulating
IP Logical ANDGEU Greater Than or Equal Accumulating Unsigned
IP Logical ANDLT Less Than Accumulating
IP Logical ANDLTU Less Than Accumulating Unsigned
IP Logical ANDNE Not Equal Accumulating
IP Logical ANDT Bit Logical AND
IP Logical ANDN Bitwise AND-Not
IP Logical ANDNT Bit Logical AND-Not
IP Coprocessor 0 BMERGE Bit Merge
IP Coprocessor 0 BSPLIT Bit Split
IP Arithmetic CADD Conditional Add
IP Arithmetic CADDN Conditional Add-Not
IP Count CLO Count Leading Ones
IP Count CLOH Count Leading Ones in Packed Half-words
IP Count CLS Count Leading Signs
IP Count CLSH Count Leading Signs in Packed Half-words
IP Count CLZ Count Leading Zeros
IP Count CLZH Count Leading Zeros in Packed Half-words
IP Move CMOV (16-bit) Conditional Move (16-bit)
IP Move CMOVN (16-bit) Conditional Move-Not (16-bit)
IP Coprocessor 0 CRC32B CRC32 Byte TC162
IP Coprocessor 0 CRC32BW CRC32 (TC1.6) CRC32 Word Big-Endian TC16
IP Coprocessor 0 CRC32LW CRC32 Word Little-Endian TC162
IP Coprocessor 0 CRCN User-Defined CRC TC162
IP Arithmetic CSUB Conditional Subtract
IP Arithmetic CSUBN Conditional Subtract-Not
IP Extract DEXTR Extract from Double Register
IP Integer Divide DVADJ Divide-Adjust
IP Integer Divide DIV Divide TC16
IP Integer Divide DIVU Divide Unsigned TC16
IP Integer Divide DVINIT Divide-Initialization Word
IP Integer Divide DVINITU Divide-Initialization Word Unsigned
IP Integer Divide DVINITB Divide-Initialization Byte
IP Integer Divide DVINITBU Divide-Initialization Byte Unsigned
IP Integer Divide DVINITH Divide-Initialization Half-word
IP Integer Divide DVINITHU Divide-Initialization Half-word Unsigned
IP Integer Divide DVSTEP Divide-Step
IP Integer Divide DVSTEPU Divide-Step Unsigned
IP Compare EQ Equal
IP Compare EQB Equal Packed Byte
IP Compare EQH Equal Packed Half-word
IP Compare EQW Equal Packed Word
IP Compare EQANYB Equal Any Byte
IP Compare EQANYH Equal Any Half-word
IP Extract EXTR Extract Bit Field
IP Extract EXTRU Extract Bit Field Unsigned
IP Compare GE Greater Than or Equal
IP Compare GEU Greater Than or Equal Unsigned
IP Extract IMASK Insert Mask
IP Extract INST Insert Bit
IP Extract INSNT Insert Bit-Not
IP Extract INSERT Insert Bit Field
IP Coprocessor 0 IXMAX Find Maximum Index
IP Coprocessor 0 IXMAXU Find Maximum Index (unsigned)
IP Coprocessor 0 IXMIN Find Minimum Index
IP Coprocessor 0 IXMINU Find Minimum Index (unsigned)
IP Control Flow JEQ Jump if Equal TC16*
IP Control Flow JGE Jump if Greater Than or Equal
IP Control Flow JGEU Jump if Greater Than or Equal Unsigned
IP Control Flow JGEZ (16-bit) Jump if Greater Than or Equal to Zero (16-bit)
IP Control Flow JGTZ (16-bit) Jump if Greater Than Zero (16-bit)
IP Control Flow JLEZ (16-bit) Jump if Less Than or Equal to Zero (16-bit)
IP Control Flow JLT Jump if Less Than
IP Control Flow JLTU Jump if Less Than Unsigned
IP Control Flow JLTZ (16-bit) Jump if Less Than Zero (16-bit)
IP Control Flow JNE Jump if Not Equal TC16*
IP Control Flow JNED Jump if Not Equal and Decrement
IP Control Flow JNEI Jump if Not Equal and Increment
IP Control Flow JNZ (16-bit) Jump if Not Equal to Zero (16-bit)
IP Control Flow JNZT Jump if Not Equal to Zero Bit
IP Control Flow JZ (16-bit) Jump if Zero (16-bit)
IP Control Flow JZT Jump if Zero Bit
IP Compare LT Less Than
IP Compare LTU Less Than Unsigned
IP Compare LTB Less Than Packed Byte
IP Compare LTBU Less Than Packed Byte Unsigned
IP Compare LTH Less Than Packed Half-word
IP Compare LTHU Less Than Packed Half-word Unsigned
IP Compare LTW Less Than Packed Word
IP Compare LTWU Less Than Packed Word Unsigned
IP Multiply Accumulate MADD Multiply-Add
IP Multiply Accumulate MADDS Multiply-Add, Saturated
IP Multiply Accumulate MADDH Packed Multiply-Add Q Format
IP Multiply Accumulate MADDSH Packed Multiply-Add Q Format, Saturated
IP Multiply Accumulate MADDQ Multiply-Add Q Format
IP Multiply Accumulate MADDSQ Multiply-Add Q Format, Saturated
IP Multiply Accumulate MADDU Multiply-Add Unsigned
IP Multiply Accumulate MADDSU Multiply-Add Unsigned, Saturated
IP Multiply Accumulate MADDMH Packed Multiply-Add Q Format Multi-precision
IP Multiply Accumulate MADDMSH Packed Multiply-Add Q Format Multi-precision, Saturated
IP Multiply Accumulate MADDRH Packed Multiply-Add Q Format with Rounding
IP Multiply Accumulate MADDRSH Packed Multiply-Add Q Format with Rounding, Saturated
IP Multiply Accumulate MADDRQ Multiply-Add Q Format with Rounding
IP Multiply Accumulate MADDRSQ Multiply-Add Q Format with Rounding, Saturated
IP Multiply Accumulate MADDSUH Packed Multiply-Add/Subtract Q Format
IP Multiply Accumulate MADDSUSH Packed Multiply-Add/Subtract Q Format Saturated
IP Multiply Accumulate MADDSUMH Packed Multiply-Add/Subtract Q Format Multi-precision
IP Multiply Accumulate MADDSUMSH Packed Multiply-Add/Subtract Q Format Multi-precision Saturated
IP Multiply Accumulate MADDSURH Packed Multiply-Add/Subtract Q Format with Rounding
IP Multiply Accumulate MADDSURSH Packed Multiply-Add/Subtract Q Format with Rounding Saturated
IP Arithmetic MAX Maximum Value
IP Arithmetic MAXU Maximum Value Unsigned
IP Arithmetic MAXB Maximum Value Packed Byte
IP Arithmetic MAXBU Maximum Value Packed Byte Unsigned
IP Arithmetic MAXH Maximum Value Packed Half-word
IP Arithmetic MAXHU Maximum Value Packed Half-word Unsigned
IP Arithmetic MIN Minimum Value
IP Arithmetic MINU Minimum Value Unsigned
IP Arithmetic MINB Minimum Value Packed Byte
IP Arithmetic MINBU Minimum Value Packed Byte Unsigned
IP Arithmetic MINH Minimum Value Packed Half-word
IP Arithmetic MINHU Minimum Value Packed Half-word Unsigned
IP Move MOV Move
IP Move MOVU Move Unsigned
IP Move MOVH Move High
IP Multiply Accumulate MSUB Multiply-Subtract
IP Multiply Accumulate MSUBS Multiply-Subtract, Saturated
IP Multiply Accumulate MSUBH Packed Multiply-Subtract Q Format
IP Multiply Accumulate MSUBSH Packed Multiply-Subtract Q Format, Saturated
IP Multiply Accumulate MSUBQ Multiply-Subtract Q Format
IP Multiply Accumulate MSUBSQ Multiply-Subtract Q Format, Saturated
IP Multiply Accumulate MSUBU Multiply-Subtract Unsigned
IP Multiply Accumulate MSUBSU Multiply-Subtract Unsigned, Saturated
IP Multiply Accumulate MSUBADH Packed Multiply-Subtract/Add Q Format
IP Multiply Accumulate MSUBADSH Packed Multiply-Subtract/Add Q Format, Saturated
IP Multiply Accumulate MSUBADMH Packed Multiply-Subtract/Add Q Format-Multi-precision
IP Multiply Accumulate MSUBADMSH Packed Multiply-Subtract/Add Q Format-Multi-precision, Saturated
IP Multiply Accumulate MSUBADRH Packed Multiply-Subtract/Add Q Format with Rounding
IP Multiply Accumulate MSUBADRSH Packed Multiply-Subtract/Add Q Format with Rounding, Saturated
IP Multiply Accumulate MSUBMH Packed Multiply-Subtract Q Format-Multi-precision
IP Multiply Accumulate MSUBMSH Packed Multiply-Subtract Q Format-Multi-precision, Saturated
IP Multiply Accumulate MSUBRH Packed Multiply-Subtract Q Format with Rounding
IP Multiply Accumulate MSUBRSH Packed Multiply-Subtract Q Format with Rounding, Saturated
IP Multiply Accumulate MSUBRQ Multiply-Subtract Q Format with Rounding
IP Multiply Accumulate MSUBRSQ Multiply-Subtract Q Format with Rounding, Saturated
IP Multiply MUL Multiply
IP Multiply MULS Multiply, Saturated
IP Multiply MULH Packed Multiply Q Format
IP Multiply MULQ Multiply Q Format
IP Multiply MULU Multiply Unsigned
IP Multiply MULSU Multiply Unsigned, Saturated
IP Multiply MULMH Packed Multiply Q Format-Multi-precision
IP Multiply MULRH Packed Multiply Q Format with Rounding
IP Multiply MULRQ Multiply Q Format with Rounding
IP Logical NAND Bitwise NAND
IP Logical NANDT Bit Logical NAND
IP Compare NE Not Equal
IP Logical NOR Bitwise NOR
IP Logical NORT Bit Logical NOR
IP Logical NOT (16-bit) Bitwise Complement NOT (16-bit)
IP Logical OR Bitwise OR
IP Logical ORANDT Accumulating Bit Logical OR-AND
IP Logical ORANDNT Accumulating Bit Logical OR-AND-Not
IP Logical ORNORT Accumulating Bit Logical OR-NOR
IP Logical ORORT Accumulating Bit Logical OR-OR
IP Logical OREQ Equal Accumulating
IP Logical ORGE Greater Than or Equal Accumulating
IP Logical ORGEU Greater Than or Equal Accumulating Unsigned
IP Logical ORLT Less Than Accumulating
IP Logical ORLTU Less Than Accumulating Unsigned
IP Logical ORNE Not Equal Accumulating
IP Logical ORT Bit Logical OR
IP Logical ORN Bitwise OR-Not
IP Logical ORNT Bit Logical OR-Not
IP Coprocessor 0 PACK Pack
IP Coprocessor 0 PARITY Parity
IP Count POPCNTW Population Count Word TC162
IP Trap and Interrupt RSTV Reset Overflow Bits
IP Arithmetic RSUB Reverse-Subtract
IP Arithmetic RSUBS Reverse-Subtract with Saturation
IP Arithmetic RSUBSU Reverse-Subtract Unsigned with Saturation
IP Arithmetic SATB Saturate Byte
IP Arithmetic SATBU Saturate Byte Unsigned
IP Arithmetic SATH Saturate Half-word
IP Arithmetic SATHU Saturate Half-word Unsigned
IP Arithmetic SEL Select
IP Arithmetic SELN Select-Not
IP Shift SH Shift
IP Shift SHEQ Shift Equal
IP Shift SHGE Shift Greater Than or Equal
IP Shift SHGEU Shift Greater Than or Equal Unsigned
IP Shift SHH Shift Packed Half-words
IP Shift SHLT Shift Less Than
IP Shift SHLTU Shift Less Than Unsigned
IP Shift SHNE Shift Not Equal
IP Shift SHANDT Accumulating Shift-AND
IP Shift SHANDNT Accumulating Shift-AND-Not
IP Shift SHNANDT Accumulating Shift-NAND
IP Shift SHNORT Accumulating Shift-NOR
IP Shift SHORT Accumulating Shift-OR
IP Shift SHORNT Accumulating Shift-OR-Not
IP Shift SHXNORT Accumulating Shift-XNOR
IP Shift SHXORT Accumulating Shift-XOR
IP Shift SHA Arithmetic Shift
IP Shift SHAH Arithmetic Shift Packed Half-words
IP Shift SHAS Arithmetic Shift with Saturation
IP Arithmetic SHUFFLE Byte Shuffle TC162
IP Arithmetic SUB Subtract
IP Arithmetic SUBB Subtract Packed Byte
IP Arithmetic SUBH Subtract Packed Half-word
IP Arithmetic SUBC Subtract With Carry
IP Arithmetic SUBS Subtract Signed with Saturation
IP Arithmetic SUBSU Subtract Unsigned with Saturation
IP Arithmetic SUBSH Subtract Packed Half-word with Saturation
IP Arithmetic SUBSHU Subtract Packed Half-word Unsigned with Saturation
IP Arithmetic SUBX Subtract Extended
IP Coprocessor 0 UNPACK Unpack Floating Point
IP Logical XNOR Bitwise XNOR
IP Logical XNORT Bit Logical XNOR
IP Logical XOR Bitwise XOR
IP Logical XOREQ Equal Accumulating
IP Logical XORGE Greater Than or Equal Accumulating
IP Logical XORGEU Greater Than or Equal Accumulating Unsigned
IP Logical XORLT Less Than Accumulating
IP Logical XORLTU Less Than Accumulating Unsigned
IP Logical XORNE Not Equal Accumulating
IP Logical XORT Bit Logical XOR
FPU Floating Point ADDF Add Float
FPU Floating Point CMPF Compare Float
FPU Floating Point DIVF Divide Float
FPU Floating Point FTOI Float to Integer
FPU Floating Point FTOIZ Float to Integer, Round towards Zero TC131
FPU Floating Point FTOQ31 Float to Fraction
FPU Floating Point FTOQ31Z Float to Fraction, Round towards Zero TC131
FPU Floating Point FTOU Float to Unsigned
FPU Floating Point FTOUZ Float to Unsigned, Round towards Zero TC131
FPU Floating Point FTOHP Single Precision to Half Precision TC162
FPU Floating Point HPTOF Half Precision to Single Precision TC162
FPU Floating Point ITOF Integer to Float
FPU Floating Point MADDF Multiply Add Float
FPU Floating Point MSUBF Multiply Subtract Float
FPU Floating Point MULF Multiply Float
FPU Floating Point Q31TOF Fraction to Floating-point
FPU Floating Point QSEEDF Inverse Square Root Seed
FPU Floating Point SUBF Subtract Float
FPU Floating Point UPDFL Update Flags
FPU Floating Point UTOF Unsigned to Floating-point

See Also

External Links

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